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PD70201 Datenblatt(PDF) 4 Page - Microsemi Corporation |
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PD70201 Datenblatt(HTML) 4 Page - Microsemi Corporation |
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4 / 20 page ![]() _________________________________________________________________________________________________________ Copyright © 2015 Microsemi Page 4 of 20 Rev.2.0, 17-Jan-2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70101 / PD70201 Datasheet Pin Number PD70101 Pin Name PD70201 Pin Name Description 23 VL VL 5V (GND reference) internal LDO Output. Connect a 1µF or higher ceramic cap from VL to GND. 24 SG SG Secondary Gate Driver. Output is the compliment of PG output. Leave open (NC) if not used. SG is low when in Low Power Skip Mode. 25 PGND PGND This is the Power Ground. Connect to a local PGND plane. Input, VCC decoupling capacitors, PG and SG drivers. Primary current sense resistor return to this PGND. 26 CSN CSN Negative Input of the Current Sense Amplifier. Kelvin connect to the PGND side of the primary current sense resistor. 27 CSP CSP Possitive Input of the Current Sense Amplifier. Kelvin connect to the Non- PGND side of the primary current sense resistor. 28 PG PG Primary Gate Driver. Connect to the gate of the primary side Power MOSFET, directly or via a resistor. 29 VH VH 5V High side ( VCC reference) internal LDO Output. Connect a 0.1µF or higher ceramic cap from VH to VCC. 30 VCC VCC Input Supply to the DC-DC Controller. Connect a 4.7µF or higher ceramic capacitor from this pin to PGND. Alternately an parallel combination of 1µF ceramic and an greater than 10µF electrolytic capacitor can be used. 31 VAUX VAUX Auxiliary voltage reference to VPN_OUT; this voltage can be used for DC-DC startup when operated with a bootstrapped voltage source. For applications with POE power only connect directly to VCC; for applications using multiple power sources (such as a wall adaptor), connect to VCC pin through a small, low current, 30V rated schottky diode. 32 VPP VPP This is the positive terminal of the POE input port. Connect to the positive terminal of the input bridges at the CDET positive side. EP Exposed Pad Exposed Pad Thermal Pad; electrically connected to VPN_IN. For proper thermal management should be tied to a large copper fill or plane that is electrically connected to VPN_IN. |
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