Philips Semiconductors

Product specification

74LV595

8-bit serial-in/serial or parallel-out shift register

with output latches (3-State)

1998 Apr 20

3

PIN DESCRIPTION

PIN

NUMBER

SYMBOL

FUNCTION

15, 1, 2, 3,

4, 5, 6, 7

Parallel data output

8

GND

Ground (0V)

9

Serial data output

10

MR

Master reset (active LOW)

11

Shift register clock input

12

Storage register clock input

13

OE

Output enable input (active LOW)

14

Serial data input

16

Positive supply voltage

PIN CONFIGURATION

SV00720

14

13

12

11

10

9

8

7

6

5

4

3

2

1

15

16

GND

OE

MR

FUNCTION TABLE

INPUTS

OUTPUTS

FUNCTION

OE

MR

Qn

FUNCTION

X

X

L

L

X

L

NC

A LOW level on MR only affects the shift registers

X

°

L

L

X

L

L

Empty shift register loaded into storage register

X

X

H

L

X

L

Z

Shift register clear. Parallel outputs in high-impedance OFF-states

°

X

L

H

H

NC

Logic high level shifted into shift register stage 0. Contents of all shift

register stages shifted through, e.g. previous state of stage 6 (internal

X

°

L

H

X

NC

Contents of shift register stages (internal Qn’) are transferred to the

storage register and parallel output stages

°

°

L

H

X

Contents of shift register shifted through. Previous contents of the shift

register are transferred to the storage register and the parallel output

stages

H = HIGH voltage level

L

= LOW voltage level

X = Don’t care

Z = High impedance OFF-state

NC= No change

° = LOW-to-HIGH clock transition

↓ = HIGH-to-LOW transition