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STM32H7B0IB Datenblatt(PDF) 95 Page - STMicroelectronics

Teilenummer STM32H7B0IB
Bauteilbeschribung  32-bit Arm® Cortex®-M7 280 MHz MCUs, 128-Kbyte Flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto
PDF  205 Pages
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Hersteller  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
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STM32H7B0IB Datenblatt(HTML) 95 Page - STMicroelectronics

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Symbol
Parameter
Conditions
Min(1) Typ(1) Max(1) Unit
∆VDD(CSI)
CSI oscillator frequency drift over VDD
VDD = 1.62 to 3.6 V
−0.06
-
0.06
%
tsu(CSI)
CSI oscillator startup time
-
-
1
2
µs
tstab(CSI)
CSI oscillator stabilization time (to reach ± 3 % of
fCSI)
-
-
-
4
cycle
IDD(CSI)
CSI oscillator power consumption
-
-
23
30
µA
1. Guaranteed by design, unless otherwise specified.
2. Calibrated during manufacturing tests.
3. Guaranteed by characterization results.
Low-speed internal (LSI) RC oscillator
Table 52. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSI
LSI frequency
VDD = 3.3 V, TJ = 25 °C
31,4(1)
32 32,6(1)
kHz
TJ = –40 to 110 °C, VDD = 1.62 to 3.6 V 29,76(2)
-
33,6(2)
TJ = –40 to 130 °C, VDD = 1.62 to 3.6 V 29,4(2)
-
33,6(2)
tsu(LSI)(3)
LSI oscillator startup time
-
-
80
130
µs
tstab(LSI)(3)
LSI oscillator stabilization time (5% of final
value)
-
-
120
170
IDD(LSI)(3)
LSI oscillator power consumption
-
-
130
280
nA
1. Calibrated during manufacturing tests.
2. Guaranteed by characterization results.
3. Guaranteed by design.
6.3.11
PLL characteristics
The parameters given in Table 53. PLL characteristics (wide VCO frequency range) are derived from tests
performed under temperature and VDD supply voltage conditions summarized in Table 20. General operating
conditions.
Table 53. PLL characteristics (wide VCO frequency range)
Symbol
Parameter
Conditions
Min(1) Typ(1) Max(1) Unit
fPLL_IN
PLL input clock
-
2
-
16
MHz
PLL input clock duty cycle
-
10
-
90
%
fPLL_P_OUT PLL multiplier output clock P, Q, R
VOS0
1
-
280(2)
MHz
VOS1
1
-
225(2)
VOS2
1
-
160(2)
VOS3
1
-
88(2)
fVCO_OUT PLL VCO output
-
128
-
560(3)
tLOCK
PLL lock time
Normal mode
-
45
100(3)
µs
Sigma-delta mode (fPLL_IN ≥ 8 MHz)
-
60
120(3)
Jitter
Cycle-to-cycle jitter
fVCO_OUT = 128 MHz
-
60
-
±ps
fVCO_OUT = 200 MHz
-
50
-
fVCO_OUT = 400 MHz
-
20
-
STM32H7B0xB
Operating conditions
DS13196 - Rev 7
page 95/205



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