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70V7319S

High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Description:

The IDT70V7319 is a high-speed 256Kx18 (4Mbit) synchronous

Bank-Switchable Dual-Ported SRAM organized into 64 independent

4Kx18 banks. The device has two independent ports with separate

control,address,andI/Opinsforeachport,allowingeachporttoaccess

any 4Kx18 memory block not already accessed by the other port.

Accesses by the ports into specific banks are controlled via the bank

address pins under the user's direct control.

Registersoncontrol,data,andaddressinputsprovideminimalsetup

and hold times. The timing latitude provided by this approach allows

systems to be designed with very short cycle times. With an input data

Pin Configuration(1,2,3,4)

NOTES:

1. AllVDDpinsmustbeconnectedto3.3Vpowersupply.

2. AllVDDQpinsmustbeconnectedtoappropriatepowersupply:3.3VifOPTpinforthatportissettoVIH(3.3V),and2.5VifOPTpinforthatportis

settoVIL(0V).

3. AllVSSpinsmustbeconnectedtogroundsupply.

4. Packagebodyisapproximately15mmx15mmx1.4mmwith0.8mmballpitch.

5. Thispackagecodeisusedtoreferencethepackagediagram.

6. Thistextdoesnotindicateorientationoftheactualpart-marking.

register, the IDT70V7319 has been optimized for applications having

unidirectional or bidirectional data flow in bursts. An automatic power

downfeature,controlledbyCE0andCE1,permitstheon-chipcircuitryof

each porttoenteraverylowstandbypowermode.Thedualchipenables

alsofacilitatedepthexpansion.

The70V7319cansupportanoperatingvoltageofeither3.3Vor2.5V

ononeorbothports,controllablebytheOPTpins.Thepowersupplyfor

the core of the device(VDD) remains at 3.3V. Please refer also to the

functionaldescriptiononpage18.

A17

VSS

B17

NC

C17

VSS

D17

I/O7R

E16

VSS

E17

NC

D16

I/O7L

C16

NC

B16

I/O8L

A16

NC

A15

OPTL

B15

VDDQR

C15

I/O8R

D15

VDDQL

E15

NC

E14

I/O6L

D14

NC

D13

VDD

C12

A6L

C14

VDD

B14

VSS

A14

A0L

A12

CNTENL

B12

A5L

C11

R/

WL

D12

A3L

D1 1

REPEATL

C10

VSS

B11

ADSL

A11

CLKL

D8

LBL

C8

UBL

A9

NC

D9

VDD

C9

CE1L

B9

CE0L

D10

OEL

C7

A10L

B8

NC

A8

A8L

B13

A1L

A13

A4L

A10

VDD

D7

A7L

B7

A9L

A7

BA0L

B6

BA1L

C6

BA2L

D6

A11L

A5

NC

B5

BA5L

C5

NC

D5

BA3L

A4

TDO

B4

TDI

C4

PL/

FTL

D4

NC

A3

VSS

B3

NC

C3

VDDQR

D3

I/O10L

D2

VSS

C2

I/O9R

B2

VSS

A2

NC

A1

IO9L

B1

NC

C1

VDDQL

D1

NC

E1

I/O11L

E2

NC

E3

VDDQR

E4

I/O10R

F1

VDDQL

F2

I/O11R

F3

NC

F4

VSS

G1

NC

G2

VSS

G3

I/O12L

G4

NC

H1

VDD

H2

NC

H3

VDDQR

H4

I/O12R

J1

VDDQL

J2

VDD

J3

VSS

J4

VSS

K1

I/O14R

K2

VSS

K3

I/O13R

K4

VSS

L1

NC

L2

I/O14L

L3

VDDQR

L4

I/O13L

M1

VDDQL

M2

NC

M3

I/O15R

M4

VSS

N1

NC

N2

VSS

N3

NC

N4

I/O15L

P1

I/O16R

P2

I/O16L

P3

VDDQR

P4

NC

R1

VSS

R2

NC

R3

I/O17R

R4

TCK

T1

NC

T2

I/O17L

T3

VDDQL

T4

TMS

U1

VSS

U2

NC

U3

PL/

FTR

U4

NC

P5

TRST

R5

BA5R

U6

A11R

P12

CNTENR

P8

A8R

U10

OER

P9

NC

R8

NC

T8

UBR

U9

VDD

P10

VDD

T11

R/

WR

U8

LBR

P11

CLKR

R12

A5R

T12

A6R

U12

A3R

P13

A4R

P7

BA0R

R13

A1R

T13

A2R

U13

A0R

R6

BA1R

T5

NC

U7

A7R

U14

VDD

T14

VSS

R14

VSS

P14

NC

P15

I/O1L

R15

VDDQL

T15

NC

U15

OPTR

U16

NC

U17

I/O0L

T16

VSS

T17

NC

R17

VDDQR

R16

I/O0R

P17

NC

P16

VSS

N17

I/O2L

N16

NC

N15

VDDQL

N14

I/O1R

M17

VDDQR

M16

I/O2R

M15

NC

M14

VSS

L17

I/O4L

L16

VSS

L15

I/O3L

L14

NC

K17

VSS

K16

I/O4R

K15

VDDQL

K14

I/O3R

J17

VDDQR

J16

VSS

J15

VDD

J14

VSS

H17

I/O5R

H16

VSS

H15

NC

H14

VDD

G17

NC

G16

I/O5L

G15

VDDQL

G14

NC

F17

VDDQR

F16

NC

F14

VSS

70V7319

BF208(5)

208-Pin fpBGA

Top View(6)

F15

I/O6R

R9

CE0R

R11

ADSR

T6

BA2R

T9

CE1R

A6

BA4L

B10

VSS

C13

A2L

P6

BA4R

R10

VSS

R7

A9R

T10

VSS

T7

A10R

U5

BA3R

5629 drw 02c

U11

REPEATR