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M95M02-DFMN5P/KF Datenblatt(PDF) 12 Page - STMicroelectronics

Teilenummer M95M02-DFMN5P/KF
Bauteilbeschribung  2-Mbit serial SPI bus EEPROM
PDF  45 Pages
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Hersteller  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
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M95M02-DFMN5P/KF Datenblatt(HTML) 12 Page - STMicroelectronics

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6.1
Write enable (WREN)
The write enable latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this
is to send a write enable instruction to the device.
As shown in Figure 8, to send this instruction to the device, chip select (S) is driven low, and the bits of the
instruction byte are shifted in, on serial data input (D). The device then enters a wait state. It waits for the device
to be deselected by chip select (S) being driven high.
Figure 8. Write enable (WREN) sequence
C
D
Q
2
1
3
4
5
6
7
High impedance
0
Instruction
S
M95M02-DR M95M02-DF
Write enable (WREN)
DS7024 - Rev 13
page 12/45



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