9.2.1.1 Design Requirements

The design requirements for the application driving the ADS127L11 ADC are listed in the following table.

Table 9-1. Design Parameters

PARAMETER

VALUE

Differential-to-differential conversion

VINDIFF to VOUTDIFF

Supply voltages

VS± = ±15 V, LVDD = 5 V, LVSS = GND, VREF = 4.096 V

Full-scale range of ADC

FSR = ± 4.096 V

Data rate of ADC

fDATA = 187.5 kSPS

ADC filter configuration

(1) High-speed mode, Sinc4 filter, OSR = 64

(2) High-speed mode, Wideband filter, OSR = 64

PGA gain

See Table 9-2 and Table 9-3

Signal frequency

Tested at fIN = 1 kHz

RC kickback filter(1)

RFIL = 47.4 Ω, CDIFF = 560 pF, CCM = 51 pF

(1)

A trade-off must be considered between THD, frequency response and drift. The differential current

drift into the ADC can interact with the filter resistors and result in higher drift errors. However, lower

resistance degrades the phase margin of the PGA855. For low drift applications, keep RFIL < 50 Ω.

9.2.1.2 Detailed Design Procedure

Table 9-2 and Table 9-3 show the typical signal-to-noise (SNR) and total harmonic distortion (THD) of the

PGA855 driving the ADS127L11 delta-sigma ADC using a sinc4 or wideband filter. Figure 9-2 and Figure 9-3

show the respective FFT plots. For the SNR and THD measurements, a 1-kHz differential signal is applied. The

signal amplitude is adjusted to produce a PGA855 output at –0.2 dBFS of the ADC full-scale range. For a list of

the equivalent input voltage amplitude signals for the different PGA855 gain configurations, see Table 9-2 and

Table 9-3.

The R-C-R differential low-pass filter at the input of the instrumentation amplifier helps reduce EMI/RFI high-

frequency extrinsic noise. This filter can be customized per the bandwidth and application requirements. This

design example (see Figure 9-1) suggests a filter with the capacitor ratio of CIN_DIFF = 10 × CIN_CM. Using the

10-to-1 ratio for differential capacitor CIN_DIFF versus common-mode capacitors CIN_CM offers good differential

and common-mode noise rejection, and this arrangement tends to be less sensitive to the tolerance variation

and mismatch of the filter capacitors.

The feedback capacitor, CFB, is in parallel with the PGA855 output-stage 5-kΩ feedback resistors to implement

additional noise filtering. The internal resistors have ±15 % absolute resistance variation, and this variation must

be taken in to account when implementing noise filtering. In this example, CFB is set to 25 pF, providing a typical

f–3dB corner frequency of 1 MHz. The estimated minimum f–3dB corner frequency for this circuit is approximately

938 kHz when accounting for the feedback-resistor variation.

The filter at the ADS127L11 inputs works as a charge reservoir to filter the sampled input of the ADC. The

charge reservoir reduces the instantaneous charge demand of the amplifier, maintaining low distortion and low

gain error that otherwise can degrade because of incomplete amplifier settling. The ADC input filter values are

RFIL = 47.4 Ω, CDIFF = 560 pF, and CCM = 51 pF.

High-grade COG (NPO) are used everywhere in the signal path (CIN_DIFF, CIN_CM, CFB, CDIFF, CCM) for

low distortion. Among ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best

capacitance accuracy. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable

electrical properties over voltage, frequency, and temperature changes.

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