TLK2201AI datasheet(12/21 Pages) TI

12 / 21 page

TLK2201A, TLK2201AI

ETHERNET TRANSCEIVERS

SLLS572 – JUNE 2003

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

transmitter/receiver characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Vod=|TxD TxN|

Rt = 50

Ω

600

850

1100

Vod = |TxD–TxN|

Rt = 75

Ω

800

1050

1200

V()

Transmit common mode voltage range

Rt = 50

Ω

1000

1250

1400

V(cm)

Transmit common mode voltage range

Rt = 75

Ω

1000

1250

1400

Receiver Input voltage requirement,

Vid = |RxP – RxN|

200

1600

Receiver common mode voltage range,

(RxP + RxN)/2

1000

1250

2250

Ilkg(R)

Receiver input leakage current

–350

350

µA

Receiver input capacitance

t(TJ)

Serial data total jitter (peak-to-peak)

Differential output jitter, Random

+ deterministic, PRBS pattern,

ω = 125 MHz

0.24

t(DJ)

Serial data deterministic jitter (peak-to-peak)

Differential output jitter, PRBS

pattern,

ω = 125 MHz

0.12

tr, tf

Differential signal rise, fall time (20% to 80%)

RL = 50 Ω,

CL = 5 pF,

See Figures 7 and 8

100

250

Serial data jitter tolerance minimum required eye

opening, (per IEEE-802.3 specification)

Differential input jitter, Random

+ deterministic, R

ω = 125 MHz

0.25

Receiver data acquisition lock time from powerup

500

µs

Data relock time from loss of synchronization

1024

Bit times

td(T l t

)

Tx latency

TBI modes

See Figure 1

td(Tx latency)

Tx latency

DDR mode

Rx latency

TBI modes

See Figure 6

td(Rx latency)

Rx latency

DDR mode

80%

50%

20%

80%

50%

20%

∼ V

80%

20%

0 V

∼ 1V

∼ –1V

TX+

TX–

VOD

Figure 7. Differential and Common-Mode

Output Voltage Definitions

5 pF

Ω

Figure 8. Transmitter Test Setup

CLOCK

80%

50%

20%

2 V

0.8 V

DATA

1.4 V

Figure 9. TTL Data I/O Valid Levels for AC Measurement

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