SC601-R datasheet(2/8 Pages) ETC1

2 / 8 page

SC-601

Data sheet

P/N 80-0207-A

The data memory is internal static RAM. The RAM is configured in 640 17-bit words. All memories are designed

to consume minimum power at a given system clock and algorithm acquisition frequency.

A flexible clock generation system enables the software to control the clock over a wide frequency range. The

implementation uses a phase-locked loop (PLL) circuit that drives the processor clock at a selectable frequency

between the minimum and maximum achievable. Selectable frequencies for the processor clock are spaced

apart in 65.536 kHz steps. The PLL clock-reference is also selectable; either a resistor-trimmed oscillator or a

crystal-referenced oscillator may be used. Internal and external clock sources are controlled separately to

provide different levels of power management.

The periphery consists of three 8-bit wide general-purpose I/O ports and one 8-bit wide dedicated input port.

The bidirectional I/O can be configured under software control as either high-impedance inputs or as totem-pole

outputs. They are controlled via addressable I/O registers. The input-only port has a programmable pullup

option (70-k

Ω minimum resistance) and a dedicated service interrupt. These features make the input port

especially useful as a key-scan interface.

A simple one-bit comparator is also included in the periphery. The comparator is enabled by a control register,

and its pin access is shared with two pins in one of the general-purpose I/O ports. Rounding out the SC-601

periphery is a built-in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive

capability. The functional block diagram gives an overview of the SC-601 functionality.

Functional Block Diagram

SC601-R Datenblatt(PDF) 2 Page - List of Unclassifed Manufacturers