AD7763 datasheet(18/32 Pages) AD

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AD7763

Rev. 0 | Page 18 of 32

READING DATA USING THE I2S INTERFACE

AD7763

(000)

MCLK

LEFT CHANNEL

RIGHT CHANNEL

DEVICE

ADDRESS

000

DEVICE

ADDRESS

001

ADR[2:0]

FSO

SH[2:0]

I2S

SH[2:0]

MCLK

SCO

SDO

SCK

3-WIRE

I2S INTERFACE

AD7763

(001)

MCLK

SH[2:0]

SDO

ADR[2:0]

I2S

The AD7763 has the capability of operating using an I2S

interface. The interface is functional only for the output of

stereo data and does not apply to writing to control registers,

programming coefficients for the digital filter, or the reading of

any information contained in the AD7763 onboard registers.

All of these operations must be undertaken using the normal

serial interface.

The I2S interface operates using two AD7763 devices. The pins

shown in Table 9 are used as the output pins for the SCK (serial

clock), SD (serial data), and WS (word select) signals for the I2S

interface.

Table 9.

SPI Pins

I2S Signals

FSO

SDO

SCO

SCK

Figure 27. Two AD7763 Devices Operating Using the I2S Interface

To enable the I2S interface, the I2S pin is set to logic high. The

Share Pins SH[2:0] of both AD7763 devices that use the I2S

interface are set to 001. The Address Pins ADR[2:0] of the two

devices must also be set to 000 and 001, respectively.

Conversion results from Device B, assigned Address 001, are

clocked out on the SD line when WS is logic high. The SD line

goes into three-state on the falling edge of the 32nd SCK after

the falling edge of WS (left channel data) and also on the falling

edge of the 32nd SCK after the rising edge of WS (right channel

data). This permits swapping of the SD bus between the left and

right channel devices without contention.

The WS and SCK signals that are used for the interface can be

taken from either AD7763 device. Note that the device that is

assigned Address 000 is defined as the left channel, and its data

is output on the SD line when WS is logic low.

The WS and SCK signals can be taken from the appropriate

pins on either of the AD7763 devices using the I2S interface.

The SD pins of both devices must be connected together, as

shown in Figure 27.

In decimate × 32 mode the I2S interface is operational only

when CDIV = 0 and SCR = 1. The interface operates for all

combinations of SCR and CDIV in all other modes of

decimation.

Data is clocked out on the SD line in accordance with Figure 28.

Because Device A is assigned Address 000, it is defined as the

left channel. The 32-bit conversion result from the left channel

is clocked out when WS is logic low, with the MSB being clocked

out first. Each 32-bit result consists of 24 data bits in twos

complement format, followed by eight status bits, as shown in

the following bit map.

The DRDY pulse still operates as in the normal serial SPI-type

interface, pulsing low immediately prior to the falling edge of

WS but having no meaning in the I2S interface specification.

DVALID

OVR

UFILTER

LPWR

FILTER_OK

ADR0

Three-

State

ST1

ST2

D21

THREE-

STATE

D22

THREE-

STATE

THREE-

STATE

D23

D21

D22

RIGHT CHANNEL

DEVICE B

(WORD n – 1)

RIGHT CHANNEL

DEVICE B

(WORD n + 1)

LEFT CHANNEL

DEVICE A

(WORD n + 2)

LEFT CHANNEL

DEVICE A

(WORD n)

D23

SCK A (O)

WS A (O)

SD (O)

ST1

ST2

Figure 28. Timing Diagram for I2S Interface

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