ICS601-21

LOW PHASE NOISE CLOCK MULTIPLIER

CLOCK MULTIPLIER

IDT® LOW PHASE NOISE CLOCK MULTIPLIER

4

ICS601-21

REV J 121412

DC Electrical Characteristics (continued)

Note 1: Outputs terminated with 50

 to VDD-2V

AC Electrical Characteristics

VDD = 3.3 V ±0.3V, Ambient Temperature 0 to +70

 C

Note 2: Input frequency limited by maximum output frequency and multiplication factor (I.e. For 16x, maximum input

frequency is 13.75 MHz).

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input High Voltage

VIH

Input select pins

2

VDD

V

Input Low Voltage

VIL

Input select pins

0.8

V

Output High Voltage

VOH

Note 1

VDD-1.4

VDD-1.0

V

Output Low Voltage

VOL

Note 1

VDD-2.0

VDD-1.7

V

Output Voltage Swing

Vswing

Peak to Peak

0.6

0.95

V

Operating Supply Current

IDD

Note 1, 125 MHz

30

45

mA

Input Capacitance

CIN

Input select pins

5

pF

On Chip Pull-up Resistor

RPU

Input select pins

510

k



Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Crystal Input Frequency

Fin

Note 2

10

27

MHz

Clock Input Frequency

Fin

Note 2, “Multiply by 6” setting

10

38

MHz

Note 2, excluding “Multiply by 6”

setting

10

31

MHz

Output Frequency

10

230

MHz

Output Rise Time

tOR

20% to 80%, no load

600

900

ps

Output Fall Time

tOF

80% to 20%, no load

900

1200

ps

Output Clock Duty Cycle

at VDD/2

45

50

55

%

Maximum Absolute Jitter, short

term, 125 MHz

No load

±50

±75

ps

Maximum Jitter, one sigma,

125 MHz (x5)

No load

12

20

ps

Phase Noise, relative to carrier,

125 MHz (x5)

100 Hz offset

-90

-94

dBc/Hz

Phase Noise, relative to carrier,

125 MHz (x5)

1 kHz

-116

-120

dBc/Hz

Phase Noise, relative to carrier,

125 MHz (x5)

10 kHz offset

-118

-122

dBc/Hz

Phase Noise, relative to carrier,

125 MHz (x5)

100 kHz offset

-115

-119

dBc/Hz