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ICS950211 Datenblatt(PDF) 6 Page - Renesas Technology Corp |
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ICS950211 Datenblatt(HTML) 6 Page - Renesas Technology Corp |
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6 / 22 page ![]() 6 Integrated Circuit Systems, Inc. ICS950211 0465E—05/17/05 Byte 1: Output Control Register (1 = enable, 0 = disable) Byte 3: Output Control Register (1 = enable, 0 = disable) Byte 2: Output Control Register (1 = enable, 0 = disable) Byte 4: Output Control Register (1 = enable, 0 = disable) t i B# n i PD W Pn o i t p i r c s e D 7 t i B8 31 T O D _ Z H M 8 4 6 t i B9 31 B S U _ z H M 8 4 5 t i B- 1 e l b a s i D = 0 , e l b a n E = 1 t c e t e d t f i h s r a e g t e s e R 4 t i B- 0 ) e l b a T l o r t n o C . q e r F c n y s A e e S ( 0 t i b l o r t n o c . q e r f c n y s A 3 t i B5 30 , K L C _ H C V / 1 _ 6 6 V 3z H M 8 4 = 1 , z H M 6 6 . 6 6 = ) t l u a f e d ( 2 t i B7 1 2 F _ K L C I C P 1 t i B6 1 1 F _ K L C I C P 0 t i B5 1 0 F _ K L C I C P t i B# n i PD W Pn o i t p i r c s e D 7 t i B5 4 , 4 41 2 C / T U P C 6 t i B9 4 , 8 41 1 C / T U P C 5 t i B2 5 , 1 51 0 C / T U P C 4 t i B- X k c a b d a e R 4 S F 3 t i B- X k c a b d a e R 3 S F 2 t i B- X k c a b d a e R 2 S F 1 t i B- X k c a b d a e R 1 S F 0 t i B- X k c a b d a e R 0 S F t i B# n i PD W Pn o i t p i r c s e D 7 t i B- X ) k c a b d a e R ( L E S T L U M 6 t i B8 11 6 _ K L C I C P 5 t i B7 11 5 _ K L C I C P 4 t i B6 11 4 _ K L C I C P 3 t i B3 11 3 _ K L C I C P 2 t i B2 11 2 _ K L C I C P 1 t i B1 11 1 _ K L C I C P 0 t i B0 11 0 _ K L C I C P Notes: 1. PWD = Power on Default 2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC off, and external resistor termination will bring CPUCLKC low. t i B# n i PD W Pn o i t p i r c s e D 7 t i B- 1 ) e l b a T l o r t n o C . q e r F . c n y s A e e S ( 1 t i b l o r t n o c . q e r f . c n y s A 6 t i B- X d e v r e s e R 5 t i B3 31 0 _ 6 6 V 3 4 t i B5 31 K L C _ H C V / 1 _ 6 6 V 3 3 t i B4 21 5 _ 6 6 V 3 2 t i B3 21 4 _ 6 6 V 3 1 t i B2 21 3 _ 6 6 V 3 0 t i B1 21 2 _ 6 6 V 3 |
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