ceramic capacitor with the same ESR value. Also, the ESR of a typical tantalum increases at approximately 2:1

as the temperature goes from 25°C down to –40°C, so some guard band must be allowed.

8.2.2.5 Remote Capacitor Operation

To ensure stability, the LP5912-EP requires at least a 1-μF capacitor at the OUT pin. There is no strict

requirement for the location of the output capacitor in regards to the LDO OUT pin; the output capacitor can

be located 5 cm to 10 cm away from the LDO. This flexibility means that there is no need to have a special

capacitor close to the OUT pin if there are already respective capacitors in the system. This placement flexibility

requires that the output capacitor be connected directly between the LP5912-EP OUT pin and GND pin with no

vias. This remote capacitor feature can help designers minimize the number of capacitors in the system.

As a good design practice, keep the wiring parasitic inductance at a minimum. Thus, use traces that are as wide

as possible from the LDO output to the capacitors, keeping the LDO output trace layer as close to ground layer

as possible and avoiding vias on the path. If there is a need to use vias, implement as many vias as possible

between the connection layers. Keep parasitic wiring inductance less than 35 nH. For applications with fast load

transients, use an input capacitor equal to (or larger than) the sum of the capacitance at the output node for the

best load-transient performance.

8.2.2.6 Power Dissipation

Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is

critical to ensuring reliable operation. Device power dissipation can be calculated with Equation 1, and depends

on input voltage, output voltage, and load conditions of the design.

PD(MAX) = (VIN(MAX) – VOUT) × IOUT

(1)

Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available

voltage drop option that is greater than the dropout voltage (VDO). However, keep in mind that higher voltage

drops result in better dynamic (that is, PSRR and transient) performance.

On the WSON (DRV) package, the primary conduction path for heat is through the exposed power pad into the

PCB. To ensure the device does not overheat, connect the exposed pad (through thermal vias) to an internal

ground plane with an appropriate amount of copper PCB area.

According to Equation 2 or Equation 3, power dissipation and junction temperature are most often related by the

junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of

the ambient air (TA):

TJ(MAX) = TA(MAX) + (RθJA × PD(MAX))

(2)

PD = (TJ(MAX) – TA(MAX)) / RθJA

(3)

Unfortunately, this RθJA is highly dependent on the heat-spreading capability of the particular PCB design,

and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA

recorded in the Thermal Information table is determined by the specific EIA/JEDEC JESD51-7 standard for PCB

and copper-spreading area, and is to be used only as a relative measure of package thermal performance.

For a well-designed thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal

resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink.

www.ti.com

LP5912-EP

SNVSC57 – SEPTEMBER 2022

Copyright © 2022 Texas Instruments Incorporated

Submit Document Feedback

21

Product Folder Links: LP5912-EP