LM1771SSDX datasheet(13/18 Pages) NSC

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MOSFET Selection (Continued)

20189034

It can be seen that the average output voltage (V

OUT_AC-

TUAL

) is higher than the output voltage (V

OUT_SET) that was

calculated by the earlier equation by exactly half the output

voltage ripple. The output voltage that is targeted for regu-

lation may then be appended according to the voltage ripple.

This can be seen below:

OUT_ACTUAL=VOUT_SET +

⁄2

∆V

OUT =VOUT_SET +

⁄2

∆I

L x

ESR

Efficiency Calculations

One of the most important parameters to calculate during the

design stage is the expected efficiency of the system. This

can help determine optimal FET selection and can be used

to calculate expected temperature rise of the individual com-

ponents. The individual losses of each component are bro-

ken down and the equations are listed below:

QUIESCENT CURRENT

The quiescent current consumed by the LM1771 is one of

the major sources of loss within the controller. However, from

a system standpoint this is usually less than 0.5% of the

overall efficiency. Therefore, it could easily be omitted but is

shown for completeness:

IQ =VIN xIQ

CONDUCTION LOSS

There are three losses associated with the external FETs.

From the DC standpoint there is the I-squared R loss,

caused by the on resistance of the FET. This can be mod-

eled for the PMOS by:

P_COND =DxRDSON_PMOS xIOUT

and the NMOS by:

N_COND =(1-D)xRDSON_NMOS xIOUT

SWITCHING LOSS

The next loss is the switching loss that is caused by the need

to charge and discharge the gate capacitance of the FETs

every cycle. This can be approximated by:

P_SWITCH =VIN xQg_PMOS xfSW

for the PMOS, and the same approach can be adapted for

the NMOS:

N_SWITCH =VIN xQg_NMOS xfSW

TRANSITIONAL LOSS

The last FET power loss is the transitional loss. This is

caused by switching the PMOS while it is conducting current.

This approach only models the PMOS transition, the NMOS

loss is considered negligible because it has minimal drain to

source voltage when it switches due to the conduction of the

body diode. Therefore the transitional loss of the PMOS can

be modeled by:

P_TRANSITIONAL =0.5xVIN xIOUT xfSW x(tr +tf)

r and tf are the rise and fall times of the FET and can be

found in their corresponding datasheet. Typically these num-

bers are simulated using a 6

Ω drive, which corresponds well

to the LM1771. Given this, no adjustment is needed.

DCR LOSS

The last source of power loss in the system that needs to be

calculated is the loss associated with the inductor resistance

(DCR) which can be calculated by:

DCR =RDCR xIOUT

EFFICIENCY

The efficiency,

η, can then be calculated by summing all the

power losses and then using the equation below:

Thermals

By breaking down the individual power loss in each compo-

nent it makes it easy to determine the temperature rise of

each component. Generally the expected temperature rise

of the LM1771 is extremely low as it is not in the power path.

Therefore the only two items of concern are the PMOS and

the NMOS. The power loss in the PMOS is the sum of the

conduction loss and transitional loss, while the NMOS only

has conduction loss. It is assumed that any loss associated

with the body diode conduction during the dead-time is

negligible.

For completeness of design it is important to watch out for

the temperature rise of the inductor. Assuming the inductor is

kept out of saturation the predominant loss will be the DC

copper resistance. At higher frequencies, depending on the

core material, the core loss could approach or exceed the

DCR losses. Consult with the inductor manufacturer for ap-

propriate temp curves based on current.

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