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HM64YLB36514 Datenblatt(PDF) 6 Page - Renesas Technology Corp

Teilenummer HM64YLB36514
Bauteilbeschribung  16M Synchronous Late Write Fast Static RAM (512-kword36-bit, Register-Latch Mode)
PDF  22 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HM64YLB36514 Datenblatt(HTML) 6 Page - Renesas Technology Corp

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HM64YLB36514 Series
Rev.0.10, May.15.2003, page 6 of 22
Programmable Impedance Output Drivers
Output buffer impedance can be programmed by terminating the ZQ pin to V
SS through a precision resistor
(RQ). The value of RQ is five times the output impedance desired. The allowable value of RQ to
guarantee impedance matching with a tolerance of 15% is 250
Ω. If the status of ZQ pin is open, output
impedance is maximum value. Maximum impedance also occurs with ZQ connected to V
DDQ.
The
impedance update of the output driver occurs when the SRAM is in high-Z. Write and deselect operations
will synchronously switch the SRAM into and out of high-Z, therefore will trigger an update. The user
may choose to invoke asynchronous
G updates by providing a G setup and hold about the K clock, to
guarantee the proper update. At power up, the output buffer is in high-Z. It will take 4,096 cycles for the
impedance to be completely updated.



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