CY7C016-35AI datasheet(11/16 Pages) CYPRESS

Teilenummer	CY7C016-35AI

Bauteilbeschribung	16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy

PDF	16 Pages

Scroll/Zoom	100%

Hersteller	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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11 / 16 page

CY7C006

CY7C016

Notes:

29. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.

30. tHA depends on which enable pin (CEL or R/WL) is deasserted first.

31. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.

Switching Waveforms (continued)

ADDRESS MATCH

tPS

tBLC

tBHC

ADDRESS MATCH

tPS

tBLC

tBHC

CERValid First:

ADDRESSL,R

BUSYR

CE L

CE R

BUSYL

CER

CEL

ADDRESSL,R

C006-19

C006-20

CELValid First:

Busy Timing Diagram No. 1 (CE Arbitration)[29]

ADDRESS MATCH

tPS

ADDRESSL

BUSYR

ADDRESS MISMATCH

tRC or tWC

tBLA

tBHA

ADDRESSR

ADDRESS MATCH

ADDRESS MISMATCH

tPS

ADDRESSL

BUSYL

tRC or tWC

tBLA

tBHA

ADDRESSR

Right Address Valid First:

C006-21

C006-22

Left AddressValid First:

Busy Timing Diagram No. 2 (Address Arbitration)[28]

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