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CD54HC4051F3A Datenblatt(PDF) 20 Page - Texas Instruments |
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CD54HC4051F3A Datenblatt(HTML) 20 Page - Texas Instruments |
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20 / 49 page ![]() TG TG TG TG TG TG TG 3 A COMMON OUT/IN BINARY TO 1 OF 8 DECODER WITH ENABLE 11 10 9 6 E S2 S 1 S0 LOGIC LEVEL CONVERSION 8 7 GND VEE 16 VCC 13 14 15 12 1 5 2 4 A A A A A A A A 7 6 5 4 3 2 1 0 CHANNEL IN/OUT TG 20 CD54HC4051, CD74HC4051 CD54HCT4051, CD74HCT4051, CD54HC4052, CD74HC4052, CD54HCT4052 CD74HCT4052, CD54HC4053, CD74HC4053, CD54HCT4053, CD74HCT4053 SCHS122M – NOVEMBER 1997 – REVISED MAY 2019 www.ti.com Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052 CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053 Submit Documentation Feedback Copyright © 1997–2019, Texas Instruments Incorporated 8 Detailed Description 8.1 Overview The CDx4HCx4051 devices are a single 8-channel multiplexer having three binary control inputs, S0, S1, and S2 and an ENABLE input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8 inputs to the output. The CDx4HCx4052 devices are a differential 4-channel multiplexer having two binary control inputs, S0 and S1, and an ENABLE input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect the analog inputs to the outputs. The CDx4HCx4053 devices are a triple 2-channel multiplexer having three separate digital control inputs, S0, S1, and S2 and an ENABLE input. Each control input selects one of a pair of channels that are connected in a single- pole, double-throw configuration. When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs and the COMMON OUT/IN terminals are the inputs. 8.2 Functional Block Diagrams All inputs are protected by standard CMOS protection network. Figure 17. CDx4HCx4051 Functional Block Diagram |
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