ADE7169F16 datasheet(27/140 Pages) AD

27 / 140 page

Preliminary Technical Data

ADE7169F16

Rev. PrD | Page 27 of 140

EPSR

ESAG

EBAT

EBSO

EVDCIN

FPSR

FSAG

FBAT

FBSO

FVDCIN

FPSM

IPSME Addr. 0ECh

IPSMF Addr. 0F8h

ETI

EPSM

ESI

PTI

PSI

IEIP2 Addr. 0A9h

ADEAUTOCLR

EPSR

ESAG

EBAT

EVSW

EBSO

FPSR

FSAG

FBAT

FVSW

FBSO

FPSM

Pending PSM interrupt

EPSM

TRUE?

EVSW

reserved

EADE

: Not involved in PSM Interrupt signal chain

FVSW

EVDCIN

FVDCIN

Figure 10: PSM Interrupt Sources

Battery Switchover and Power Supply Restored

PSM Interrupt

The ADE7169F16 can be configured to generate a PSM

interrupt when the source of VSW changes from VDD to VBAT,

indicating battery switchover. Setting the EBSO bit in the

Power Management Interrupt Enable SFR (IPSME, 0xEC)

enables this event to generate a PSM interrupt.

The ADE7169F16 can also be configured to generate an

interrupt when the source of VSW changes from VBAT to VDD,

indicating that the VDD power supply has been restored. This

event is enabled to generate a PSM interrupt by setting the

EPSR bit in the Power Management Interrupt Enable SFR

(IPSME, 0xEC).

The flags in the Power Management Interrupt Flag SFR (IPSMF,

0xF8) for these interrupts, BSOF and PSRF are set regardless of

whether the respective enable bits have been set. The battery

switchover and power supply restore event flags, BSOF and

PSRF, are latched. These events must be cleared by writing a

zero to these bits. Bit 6 in the Peripheral Configuration SFR

(PERIPH, 0xF4), VSWSOURCE, tracks the source of VSW. The

bit is set when VSW is connected to VDD and cleared when VSW is

connected to VBAT.

VSW Monitor PSM Interrupt

The ADE7169F16 can be configured to generate a PSM

interrupt when VSW changes magnitude by more than a

configurable threshold. This threshold is set in the

Temperature and Supply Delta SFR (DIFFPROG, 0xF3) –see

Supply Voltage Measurement section. Setting the EVSW bit in

the Power Management Interrupt Enable SFR (IPSME, 0xEC)

enables this event to generate a PSM interrupt.

The VSW voltage is measured using a dedicated ADC. These

measurements take place in the background at intervals to

check the change in VSW. Conversions can also be initiated by

writing to the Start ADC Measurement SFR (ADCGO, 0xD8).

The EVSW flag will indicate that a VSW measurement is ready.

See the Supply Voltage Measurement section for details on how

VSW is measured.

VBAT Monitor PSM Interrupt

The VBAT voltage is measured using a dedicated ADC. These

measurements take place in the background at intervals to

check the change in VBAT. The BATTF bit is set when the battery

level is lower than the threshold set in the Battery detection

threshold SFR (BATVTH, 0xFA) or when a new measurement

is ready in the Battery ADC value SFR (BATADC, 0xDF) - see

Battery measurement section. Setting the EBATT bit in the

Power Management Interrupt Enable SFR (IPSME, 0xEC)

enables this event to generate a PSM interrupt.

VDCIN Monitor PSM Interrupt

The VDCIN voltage is monitored by a comparator. The FVDC bit

in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) is

set when the VDCIN input level is lower than 1.2 V. Setting the

EVDCIN bit in the Power Management Interrupt Enable SFR

ADE7169F16 Datenblatt(PDF) 27 Page - Analog Devices

ADE7169F16 Datenblatt(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL