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VL6524 Datenblatt(PDF) 63 Page - STMicroelectronics

Teilenummer VL6524
Bauteilbeschribung  VGA single-chip camera module
PDF  70 Pages
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Hersteller  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
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VL6524 Datenblatt(HTML) 63 Page - STMicroelectronics

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VL6524/VS6524
Electrical characteristics
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13.4.4
Parallel data interface timing
VL6524/VS6524 contains a parallel data output port (D[7:0]) and associated qualification
signals (HSYNC, VSYNC, PCLK and FSO).
This port can be enabled and disabled (tri-stated) to facilitate multiple camera systems or
bit-serial output configurations. The port is disabled (high impedance) upon reset.
Figure 35.
Parallel data output video timing
13.5
ESD handling characteristics
Table 39.
Parallel data interface timings
Symbol
Description
Conditions
Min.
Typ.
Max.
Unit
fPCLK
PCLK frequency
26
MHz
tPCLKL
PCLK low width
10
ns
tPCLKH
PCLK high width
10
ns
tDV
PCLK to output valid
-5
5
ns
tPCLKL
tPCLKH
1/fPCLK
PCLK
D[0:7]
HSYNC
polarity = 0
tDV
Valid
VSYNC
Table 40.
ESD handling characteristics
Test
Criteria
Unit
ESD Machine Model
150
V
ESD Human body
1.5
kV



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