Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

7. Functional description

Table 3. Function table

H = HIGH voltage state; L = LOW voltage state; ↑ = LOW-to-HIGH transition;

X = don’t care; NC = no change; Z = high-impedance OFF-state.

Control

Input Output

SHCP STCP OE

MR

DS

Q7S

Qn

Function

X

X

L

L

X

L

NC

a LOW-level on MR only affects the shift registers

X

↑

L

L

X

L

L

empty shift register loaded into storage register

X

X

H

L

X

L

Z

shift register clear; parallel outputs in high-impedance OFF-state

↑

X

L

H

H

Q6S

NC

logic HIGH-level shifted into shift register stage 0. Contents of all

shift register stages shifted through, e.g. previous state of stage 6

(internal Q6S) appears on the serial output (Q7S).

X

↑

L

H

X

NC

QnS

contents of shift register stages (internal QnS) are transferred to the

storage register and parallel output stages

↑

↑

L

H

X

Q6S

QnS

contents of shift register shifted through; previous contents of the

shift register is transferred to the storage register and the parallel

output stages

SHCP

DS

STCP

MR

OE

Q0

Q1

Q6

Q7

Q7S

Z-state

Z-state

Z-state

Z-state

mna556

Fig. 8. Timing diagram

74HC_HCT595

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 11 — 10 September 2021

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