8

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SEMICONDUCT OR

FIGURE 7. HC THREE-STATE PROPAGATION DELAY

WAVEFORM

FIGURE 8. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

NOTE:

FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

50%

10%

90%

GND

10%

90%

50%

50%

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS

ENABLED

OUTPUTS

DISABLED

OUTPUTS

ENABLED

6ns

6ns

0.3

2.7

GND

3V

10%

90%

1.3V

1.3V

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS

ENABLED

OUTPUTS

DISABLED

OUTPUTS

ENABLED

6ns

6ns

1.3

IC WITH

THREE-

STATE

OUTPUT

OTHER

INPUTS

TIED HIGH

OR LOW

OUTPUT

DISABLE

OUTPUT

50pF

CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573