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MP2192 Datenblatt(PDF) 17 Page - Monolithic Power Systems

Teilenummer MP2192
Bauteilbeschribung  2A, 2.5V to 5.5V, Synchronous Step-Down Converter with 25μA IQ in CSP Package
PDF  22 Pages
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Hersteller  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

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MP2192
– 2A, SYNCHRONOUS STEP-DOWN CONVERTER WITH 25µA IQ
MP2192 Rev. 1.0
MonolithicPower.com
17
5/12/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2021 MPS. All Rights Reserved.
The worst-case condition occurs at VIN = 2VOUT,
calculated with Equation (6):
LOAD
C1
I
I
2
(6)
For simplification, choose an input capacitor
with an RMS current rating greater than half of
the maximum load current.
The
input
capacitor
can
be
electrolytic,
tantalum, or ceramic. When using electrolytic or
tantalum capacitors, add a small, high-quality,
0.1μF ceramic capacitor as close to the IC as
possible.
When
using
ceramic
capacitors,
ensure that they have enough capacitance to
provide a sufficient charge to prevent excessive
voltage ripple at the input. The input voltage
ripple caused by the capacitance can be
estimated with Equation (7):
LOAD
OUT
OUT
IN
IN
SW
IN
I
V
V
V1
f
C1
V
V



(7)
Selecting the Output Capacitor
The output capacitor (C2) stabilizes the DC
output voltage. Low-ESR ceramic capacitors
are recommended to limit the output voltage
ripple. Estimate the output voltage ripple with
Equation (8):
OUT
OUT
OUT
ESR
SW
1
IN
SW
VV
1
V
1
R
f
L
V
8 f
C2




 
(8)
Where L1 is the inductor value, and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
When
using
ceramic
capacitors,
the
capacitance dominates the impedance at the
switching frequency and causes most of the
output voltage ripple. For simplification, the
output voltage ripple can be estimated with
Equation (9):
OUT
OUT
OUT
2
SW
1
IN
VV
ΔV1
8 f
L
C2
V

 

 

(9)
For tantalum or electrolytic capacitors, the ESR
dominates the impedance at the switching
frequency. For simplification, the output ripple
can be calculated with Equation (10):
OUT
OUT
OUT
ESR
IN
SW
1
VV
ΔV
1
R
f
L
V

 


(10)
The characteristics of the output capacitor also
affect the stability of the regulation system.
Design Example
Table 3 lists a design example following the
application guidelines for the specifications
below.
Table 3: Design Example
VIN
5V
VOUT
1.2V
fSW
1100kHz
For the detailed application schematic, see
Figure
11
on
page
19.
For
the
typical
performance and circuit waveforms, see the
Typical Performance Characteristics section on
page 6. For more device applications, refer to
the related evaluation board datasheets.



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