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RT4841 Datenblatt(PDF) 14 Page - Richtek Technology Corporation

Teilenummer RT4841
Bauteilbeschribung  5A Synchronous Boost Converter with Output Isolation MOS
PDF  16 Pages
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Hersteller  RICHTEK [Richtek Technology Corporation]
Direct Link  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT4841 Datenblatt(HTML) 14 Page - Richtek Technology Corporation

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RT4841
14
DS4841-00 May 2021
www.richtek.com
©
Copyright
2021 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
Figure 2. Derating Curve of Maximum Power Dissipation
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
025
50
75
100
125
Ambient Temperature (°C)
Four-Layer PCB
Layout Considerations
For high frequency switching power supplies, the PCB
layout is important to get good regulation, high efficiency
and stability. The following descriptions are the guidelines
for better PCB layout.
 For good regulation, place the power components as
close as possible. The traces should be wide and short
enough especially for the high current output loop.
 The feedback voltage divider resistors must be near the
feedback pin. The divider center trace must be shorter
and the trace must be kept away from any switching
nodes.
 The compensation circuit should be kept away from the
power loops and be shielded with a ground trace to
prevent any noise coupling.
 Minimize the size of the SW node and keep it wide and
shorter. Keep the SW node away from the FB.
 The exposed pad of the chip should be connected to a
strong ground plane for maximum thermal consideration.
SWI
PGND
1
2
3
4
5
15
14
13
20
19
18
12
11
17
16
GND
NC
GND
SWO
SWO
GND
VIN
PGND
BT
SW
PGND
Place the power
components as close to
the IC as possible. The
traces should be wide
and short especially for
the high current loop.
The exposed pad of
the chip should be
connected to ground
plane for thermal
consideration.
GND consists of input
and output capacitor
grounds and should be
wide and short enough
to connect to a ground
plane.
Connect this pin with a
decoupling capacitor.
GND
Minimize the size of
the SW node and
keep its traces as
wide and short as
possible.
6
7
8
9
10
GND
GND
Figure 3. PCB Layout Guide



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