ST72104G datasheet(19/140 Pages) STMICROELECTRONICS

Teilenummer	ST72104G

Bauteilbeschribung	8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, IC INTERFACES

PDF	140 Pages

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Hersteller	STMICROELECTRONICS [STMicroelectronics]

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ST72104G, ST72215G, ST72216G, ST72254G

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7.2 RESET SEQUENCE MANAGER (RSM)

7.2.1 Introduction

The reset sequence manager includes three RE-

SET sources as shown in Figure 11:

External RESET source pulse

Internal LVD RESET (Low Voltage Detection)

Internal WATCHDOG RESET

These sources act on the RESET pin and it is al-

ways kept low during the delay phase.

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases

as shown in Figure 10:

Delay depending on the RESET source

4096 CPU clock cycle delay

RESET vector fetch

The 4096 CPU clock cycle delay allows the oscil-

lator to stabilise and ensures that recovery has

taken place from the Reset state.

The RESET vector fetch phase duration is 2 clock

cycles.

Figure 10. RESET Sequence Phases

Figure 11. Reset Block Diagram

RESET

DELAY

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

fCPU

RESET

RON

VDD

WATCHDOG RESET

LVD RESET

INTERNAL

RESET

ST72104G Datenblatt(PDF) 19 Page - STMicroelectronics