STR91XF_07 datasheet(30/73 Pages) STMICROELECTRONICS

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Functional overview

STR91xF

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2.25.1 DMA

A programmable DMA channel may be assigned by CPU firmware to service each timer/

counter module TIM0 and TIM1 for fast and direct transfers.

2.26

Three-phase induction motor controller (IMC)

The STR91xF provides an integrated controller for variable speed motor control applications.

Six PWM outputs are generated on high current drive pins P6.0 to P6.5 for controlling a three-

phase AC induction motor drive circuit assembly. Rotor speed feedback is provided by

capturing a tachometer input signal on pin P6.6, and an asynchronous hardware emergency

stop input is available on pin P6.7 to stop the motor immediately if needed, independently of

firmware.

The IMC unit has the following features:

●

Three PWM outputs generated using a 10-bit PWM counter, one for each phase U, V, W.

Complimentary PWM outputs are also generated for each phase.

●

Choice of classic or zero-centered PWM generation modes

●

10-bit PWM counter clock is supplied through a programmable 8-bit prescaler of the APB

clock.

●

Programmable 6-bit dead-time generator to add delay to each of the three complimentary

PWM outputs

●

8-bit repetition counter

●

Automatic rotor speed measurement with 16-bit resolution. Schmitt trigger tachometer

input with programmable edge detection

●

Hardware asynchronous emergency stop input

●

A dedicated interrupt to CPU with eight flags

2.27

External memory interface (EMI)

STR91xF devices in 128-pin packages offer an external memory bus for connecting external

parallel peripherals and memories. The EMI bus resides on ports 7, 8, and 9 and operates with

either an 8 or 16-bit data path. The configuration of 8 or 16 bit mode is specified by CPU

firmware writing to configuration registers at run-time. If the application does not use the EMI

bus, then these port pins may be used for general purpose I/O as shown in Table 3.

The EMI has the following features:

●

Supports static asynchronous memory access cycles, including page mode for non-mux

operation.

●

Four configurable memory regions, each with a chip select output (EMI_CS0n ...

EMI_CS3n)

●

Programmable wait states per memory region for both write and read operations

●

16-bit multiplexed data mode (Figure 4): 16 bits of data and 16 bits of low-order address

are multiplexed together on ports 8 and 9, while port 7 contains eight more high-order

address signals. The output signal on pin EMI_ALE is used to demultiplex the signals on

ports 8 and 9, and the polarity of EMI_ALE is programmable. The output signals on pins

EMI_BWR_WRLn and EMI_WRHn are the write strobes for the low and high data bytes

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