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WM8593 Datenblatt(PDF) 11 Page - Wolfson Microelectronics plc |
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WM8593 Datenblatt(HTML) 11 Page - Wolfson Microelectronics plc |
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11 / 98 page ![]() Product Preview WM8593 w PP Rev 1.0 January 2007 11 1. All minimum and maximum values are subject to change. 2. This resistance is selectable using VMID_SEL[1:0] – see Figure 51 for full details. 3. See p95 for details of extended input impedance configuration. MASTER CLOCK TIMING Figure 1 MCLK Timing Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, TA = +25 OC PARAMETER SYMBOL MIN TYP MAX UNIT Master Clock Timing Information MCLK System clock cycle time tMCLKY 27 120 ns MCLK Duty cycle 40:60 60:40 % MCLK Period Jitter 200 ps MCLK Rise/Fall times 10 ns Table 1 Master Clock Timing Requirements ADCMCLK/ DACMCLK1/ DACMCLK2 t MCLKY |
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