Production Data

WM8782

w

PD, August 2006, Rev 4.2

9

AUDIO INTERFACE TIMING – SLAVE MODE

Figure 3 Digital Audio Data Timing – Slave Mode

Test Conditions

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

50

ns

BCLK pulse width high

20

ns

BCLK pulse width low

20

ns

LRCLK set-up time to BCLK rising edge

10

ns

LRCLK hold time from BCLK rising edge

10

ns

DOUT propagation delay from BCLK falling edge

0

10

ns

Table 3 Digital Audio Data Timing - Slave Mode

Note:

LRCLK should be synchronous with MCLK, although the WM8782 interface is tolerant of phase variations or jitter on these

signals.