AT43USB355 datasheet(60/115 Pages) ATMEL

60 / 115 page

AT43USB355

2603G–USB–04/06

Operation

The ADC converts an analog input voltage to a 10-bit digital value through successive approx-

imation. The minimum value represents V

SSA and the maximum value represents the voltage

on the V

REF pin minus one LSB. The analog input channel is selected by writing to the MUX

bits in ADMUX. Any of the twelve ADC input pins ADC11 – 0 can be selected as single-ended

inputs to the ADC.

The ADC can operate in two modes – Single Conversion and Free Running. In Single Conver-

sion Mode, each conversion will have to be initiated by the user. In Free Running Mode, the

ADC is constantly sampling and updating the ADC Data Register. The ADFR bit in ADCSR

selects between the two available modes.

The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSR. Input channel selections

will not go into effect until ADEN is set. The ADC does not consume power when ADEN is

cleared, so it is recommended to switch off the ADC before entering power-saving sleep

modes.

A conversion is started by writing a logical “1” to the ADC Start Conversion bit, ADSC. This bit

stays high as long as the conversion is in progress and will be set to zero by the hardware

when the conversion is completed. If a different data channel is selected while a conversion is

in progress, the ADC will finish the current conversion before performing the channel change.

The ADC generates a 10-bit result, which is presented in the ADC data register, ADCH and

ADCL. When reading data, ADCL must be read first, then ADCH, to ensure that the content of

the data register belongs to the same conversion. Once ADCL is read, ADC access to data

before ADCH is read, neither register is updated and the result from the conversion is lost.

Then ADCH is read, ADC access to the ADCH and ADCL register is re enabled.

The ADC has its own interrupt that can be triggered when a conversion completes. When ADC

access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt

will trigger even if the result is lost.

Figure 23. ADC Prescaler

ADPS0

ADPS1

ADPS2

ADEN

ADC Clock Source

7-bit ADC Prescaler

Reset

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