Data Sheet

ADRF5700

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 8 of 16

Figure 4. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

D5

Parallel Control Input for the First 16 dB Attenuator Bit. See the Theory of Operation section for more information. See Figure 6 for

the interface schematic.

2

D6

Parallel Control Input for the Second 16 dB Attenuator Bit. See the Theory of Operation section for more information. See Figure 6

for the interface schematic.

3, 5 to 11, 13, 17

GND

Ground. The GND pins must be connected to the RF and DC ground of the PCB.

4

ATTIN

Attenuator Input. The ATTIN pin is DC-coupled to 0 V and AC matched to 50 Ω. No DC blocking capacitor is necessary when the RF

line potential is equal to 0 V DC. See Figure 5 for the interface schematic.

12

ATTOUT

Attenuator Output. The ATTOUT pin is DC-coupled to 0 V and AC matched to 50 Ω. No DC blocking capacitor is necessary when the

RF line potential is equal to 0 V DC. See Figure 5 for the interface schematic.

14

VSS

Negative Supply Input. See Figure 8 for the interface schematic.

15

VDD

Positive Supply Input. See Figure 7 for the interface schematic.

16

LE

Latch Enable Input. See the Theory of Operation section for more information. See Figure 6 for the interface schematic.

18

D2

Parallel Control Input for 2 dB Attenuator Bit. See the Theory of Operation section for more information. See Figure 6 for the

interface schematic.

19

D3

Parallel Control Input for 4 dB Attenuator Bit. See the Theory of Operation section for more information. See Figure 6 for the

interface schematic.

20

D4

Parallel Control Input for 8 dB Attenuator Bit. See the Theory of Operation section for more information. See Figure 6 for the

interface schematic.

EPAD

Exposed Pad. The exposed pad must be connected to the RF and DC ground of the PCB.