5

82C54

Functional Diagram

CONTROL

WORD

REGISTER

READ/

WRITE

LOGIC

DATA/

BUS

BUFFER

COUNTER

2

COUNTER

1

COUNTER

0

INTERNAL BUS

CONTROL

LOGIC

CONTROL

WORD

REGISTER

STATUS

LATCH

STATUS

REGISTER

CLK n

GATE n

OUT n

OUT 2

GATE 2

CLK 2

OUT 1

GATE 1

CLK 1

OUT 0

GATE 0

CLK 0

WR

RD

CS

CE

COUNTER INTERNAL BLOCK DIAGRAM

8

Pin Description

SYMBOL

DIP PIN

NUMBER

TYPE

DEFINITION

D7 - D0

1 - 8

I/O

DATA: Bi-directional three-state data bus lines, connected to system data bus.

CLK 0

9

I

CLOCK 0: Clock input of Counter 0.

OUT 0

10

O

OUT 0: Output of Counter 0.

GATE 0

11

I

GATE 0: Gate input of Counter 0.

GND

12

GROUND: Power supply connection.

OUT 1

13

O

OUT 1: Output of Counter 1.

GATE 1

14

I

GATE 1: Gate input of Counter 1.

CLK 1

15

I

CLOCK 1: Clock input of Counter 1.

GATE 2

16

I

GATE 2: Gate input of Counter 2.

OUT 2

17

O

OUT 2: Output of Counter 2.

CLK 2

18

I

CLOCK 2: Clock input of Counter 2.

A0, A1

19 - 20

I

ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write

operations. Normally connected to the system address bus.

CS

21

I

CHIP SELECT: A low on this input enables the 82C54 to respond to RD and WR signals. RD and WR

are ignored otherwise.

RD

22

I

READ: This input is low during CPU read operations.

WR

23

I

WRITE: This input is low during CPU write operations.

24

-

decoupling.

A1

A0

SELECTS

0

0

Counter 0

0

1

Counter 1

1

0

Counter 2

1

1

Control Word Register