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HIP4080IP Datenblatt(PDF) 6 Page - Intersil Corporation

Teilenummer HIP4080IP
Bauteilbeschribung  80V/2.5A Peak, High Frequency Full Bridge FET Driver
PDF  21 Pages
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Hersteller  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

HIP4080IP Datenblatt(HTML) 6 Page - Intersil Corporation

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6
Disable Turn-off Propagation Delay
(DIS - Lower Outputs)
TDISLOW
-
45
75
-
95
ns
Disable Turn-off Propagation Delay
(DIS - Upper Outputs)
TDISHIGH
-
55
85
-
105
ns
Disable to Lower Turn-on Propagation Delay
(DIS - ALO and BLO)
TDLPLH
-
35
70
-
90
ns
Refresh Pulse Width (ALO and BLO)
TREF-PW
160
260
380
140
420
ns
Disable to Upper Enable (DIS - AHO and BHO)
TUEN
-
335
500
-
550
ns
HEN-AHO, BHO Turn-off, Propagation Delay
THEN-PHL
RHDEL = RLDEL = 10K
-
35
70
-
90
ns
HEN-AHO, BHO Turn-on, Propagation Delay
THEN-PLH
RHDEL = RLDEL = 10K
-
60
90
-
110
ns
Switching Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K,
CL = 1000pF, and TA = 25
oC, Unless Otherwise Specified (Continued)
PARAMETERS
SYMBOL
TEST CONDITIONS
TJ = 25
oC
TJ = - 40
oC
TO 125oC
UNITS
MIN
TYP
MAX
MIN
MAX
TRUTH TABLE
INPUT
OUTPUT
IN+ > IN-
HEN
DIS
ALO
AHO
BLO
BHO
X
X
10000
1
100110
0
101001
1
000010
0
001000
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1
BHB
B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30
µA out of this pin to
maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
2
HEN
High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers
(Pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can
be driven by signal levels of 0V to 15V (no greater than VDD).
3
DIS
DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to
15V (no greater than VDD).
4VSS
Chip negative supply, generally will be ground.
5
OUT
OUTput of the input control comparator. This output can be used for feedback and hysteresis.
6
IN+
Non-inverting input of control comparator. If IN+ is greater than IN- (Pin 7) then ALO and BHO are low level outputs
and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO and BHO are high level outputs and BLO
and AHO are low level outputs. DIS (Pin 3) high level will override IN+/IN- control for all outputs. HEN (Pin 2) low level
will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode, dead time in a half bridge leg
is controlled by HDEL and LDEL (Pins 8 and 9).
7
IN-
Inverting input of control comparator. See IN+ (Pin 6) description.
8
HDEL
High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of
both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no
shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V.
HIP4080
HIP4080



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