Philips Semiconductors Products

Product specification

MB2652

Dual octal transceiver/registers,

non-inverting (3-State)

August 23, 1993

3

LOGIC DIAGRAM

1D

C1

Q

nB1

nB2

nB3

nB4

nB5

nB6

nB7

nA1

nA2

nA3

nA4

nA5

nA6

nA7

DETAIL A X 7

nOEBA

nOEAB

nCPBA

nSBA

nCPAB

nSAB

nB0

1D

C1

Q

nA0

1of 8 Channels

FUNCTION TABLE

INPUTS

DATA I/O

OPERATING MODE

nOEAB

nOEBA

nCPAB

nCPBA

nSAB

nSBA

nAx

nBx

L

L

H

H

H or L

↑

H or L

↑

X

X

X

X

Input

Input

Isolation

Store A and B data

X

H

H

H

↑

↑

H or L

↑

X

**

X

X

Input

Unspecified

output*

Store A, Hold B

Store A in both registers

L

L

X

L

H or L

↑

↑

↑

X

X

X

**

Unspecified

output*

Input

Hold A, Store B

Store B in both registers

L

L

L

L

X

X

X

H or L

X

X

L

H

Output

Input

Real time B data to A bus

Stored B data to A bus

H

H

H

H

X

H or L

X

X

L

H

X

X

Input

Output

Real time A data to B bus

Store A data to B bus

H

L

H or L

H or L

H

H

Output

Output

Stored A data to B bus

Stored B data to A bus

H = High voltage level

L

= Low voltage level

X = Don’t care

↑ = Low-to-High clock transition

*

The data output function may be enabled or disabled by various signals at the nOEBA and nOEAB inputs. Data input functions are

always enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.

**

If both Select controls (nSAB and nSBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must

be staggered in order to load both registers.