COM20022I3V-HT datasheet(4/83 Pages) SMSC

4 / 83 page

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

Revision 02-27-06

Page 4

SMSC COM20022I 3V

DATASHEET

6.3.1

Sequential Access Memory ....................................................................................................................46

6.3.2

Access Speed.........................................................................................................................................47

6.3.3

Software Interface...................................................................................................................................47

6.3.4

Selecting RAM Page Size.......................................................................................................................47

6.3.5

Transmit Sequence.................................................................................................................................49

6.3.6

Receive Sequence..................................................................................................................................50

6.4

Command Chaining........................................................................................................................... 51

6.4.1

Transmit Command Chaining .................................................................................................................52

6.4.2

Receive Command Chaining ..................................................................................................................52

6.4.3

Reset Details ..........................................................................................................................................53

6.4.3.1

Internal Reset Logic.........................................................................................................................53

6.5

Initialization Sequence ...................................................................................................................... 53

6.5.1

Bus Determination ..................................................................................................................................53

6.6

Improved Diagnostics........................................................................................................................ 54

6.6.1

Normal Results: ......................................................................................................................................55

6.6.2

Abnormal Results: ..................................................................................................................................55

6.6.3

Oscillator.................................................................................................................................................55

Chapter 7

Operational Description .................................................................................................... 57

7.1

Maximum Guaranteed Ratings* ........................................................................................................ 57

7.2

DC Electrical Characteristics............................................................................................................. 57

Chapter 8

Timing Diagrams................................................................................................................ 60

Chapter 9

Appendix A ......................................................................................................................... 80

9.1

NOSYNC Bit ...................................................................................................................................... 80

9.2

EF Bit................................................................................................................................................. 80

Chapter 10

Appendix B ......................................................................................................................83

Chapter 11 ................................................................................................................................................. 83

LIST OF FIGURES

Figure 3.1 - COM20022I 3V Operation ........................................................................................................................10

Figure 5.1 - Multiplexed, 8051 - Like Bus Interface with RS-485 Interface .....................................................................17

Figure 5.2 - Non-Multiplexed, 6801-Like Bus Interface with RS-485 Interface ...............................................................18

Figure 5.3 - DREQ Pin First Assertion Timing for all DMA Modes ...............................................................................21

Figure 5.4 - Programmable Burst Mode DMA Transfer (Rough Timing) ......................................................................22

Figure 5.5 - Non-Burst Mode DMA Data Transfer Rough Timing.................................................................................23

Figure 5.6 - Burst Mode DMA Data Transfer Rough Timing ........................................................................................23

Figure 5.7 - High Speed CPU Bus Timing – Intel CPU Mode ......................................................................................25

Figure 5.8 - COM20022I 3V Network Using RS-485 Differential Transceivers...............................................................27

Figure 5.9 - Dipluse Waveform for Data of 1-1-0 ...........................................................................................................27

Figure 5.10 - Internal Block Diagram.............................................................................................................................29

Figure 6.1 - Illustration of the Effect of RTRG Bit on DMA Timing................................................................................35

Figure 6.2 - Sequential Access Operation.....................................................................................................................46

Figure 6.3 - RAM Buffer Packet Configuration ..............................................................................................................49

Figure 6.4 - Command Chaining Status Register Queue...............................................................................................51

Figure 7.1 - AC Measurements ....................................................................................................................................59

Figure 8.1 - Multiplexed Bus, 68XX-Like Control Signals; Read Cycle ........................................................................60

Figure 8.2 - Multiplexed Bus, 80XX-Like Control Signals; Read Cycle ........................................................................61

Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals; Write Cycle.........................................................................62

Figure 8.4 - Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.........................................................................63

Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................64

Figure 8.6 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................65

Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................66

Figure 8.8 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................67

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