AM29F004B datasheet(15/37 Pages) SPANSION

15 / 37 page

May 9, 2006 Am29F004B_00_E4

Am29F004B

D A TA

SH EE T

Hardware Data Protection

The command sequence requirement of unlock cycles for

programming or erasing provides data protection against

inadvertent writes (refer to the Command Definitions table).

In addition, the following hardware data protection measures

prevent accidental erasure or programming, which might oth-

erwise be caused by spurious system level signals during

VCC power-up and power-down transitions, or from system

noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any

write cycles. This protects data during VCC power-up and

power-down. The command register and all internal pro-

gram/erase circuits are disabled, and the device resets.

Subsequent writes are ignored until VCC is greater than VLKO.

The system must provide the proper signals to the control

pins to prevent unintentional writes when VCC is greater than

VLKO.

Write Pulse Glitch Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE#

do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL,

CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and

WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the

device does not accept commands on the rising edge of

WE#. The internal state machine is automatically reset to

reading array data on power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or sequences

into the command register initiates device operations. The

Command Definitions table defines the valid register

command sequences. Writing incorrect address and data

values or writing them in the improper sequence resets the

device to reading array data.

All addresses are latched on the falling edge of WE# or CE#,

whichever happens later. All data is latched on the rising edge

of WE# or CE#, whichever happens first. Refer to the appro-

priate timing diagrams in AC Characteristics on page 24.

Reading Array Data

The device is automatically set to reading array data after

device power-up. No commands are required to retrieve data.

The device is also ready to read array data after completing

an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the

device enters the Erase Suspend mode. The system can

read array data using the standard read timings, except that

if it reads at an address within erase-suspended sectors, the

device outputs status data. After completing a programming

operation in the Erase Suspend mode, the system may once

again read array data with the same exception. See Reset

Command for more information on this mode.

The system must issue the reset command to re-enable the

device for reading array data if DQ5 goes high, or while in the

autoselect mode. See the Reset Command section, next.

See also “Requirements for Reading Array Data” in the

Device Bus Operations on page 8 section for more informa-

tion. The Read Operations table provides the read

parameters, and Read Operation Timings diagram shows the

timing diagram.

Reset Command

Writing the reset command to the device resets the device to

reading array data. Address bits are don’t care for this

command.

The reset command may be written between the sequence

cycles in an erase command sequence before erasing

begins. This resets the device to reading array data. Once

erasure begins, however, the device ignores reset commands

until the operation is complete.

The reset command may be written between the sequence

cycles in a program command sequence before programming

begins. This resets the device to reading array data (also

applies to programming in Erase Suspend mode). Once pro-

gramming begins, however, the device ignores reset

commands until the operation is complete.

The reset command may be written between the sequence

cycles in an autoselect command sequence. Once in the

autoselect mode, the reset command must be written to

return to reading array data (also applies to autoselect during

Erase Suspend).

If DQ5 goes high during a program or erase operation, writing

the reset command returns the device to reading array data

(also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system

to access the manufacturer and devices codes, and deter-

mine whether or not a sector is protected. The Command

Definitions table shows the address and data requirements.

This method is an alternative to that shown in the Autoselect

Codes (High Voltage Method) table, which is intended for

PROM programmers and requires VID on address bit A9.

The autoselect command sequence is initiated by writing two

unlock cycles, followed by the autoselect command. The

device then enters the autoselect mode, and the system may

read at any address any number of times, without initiating

another command sequence.

A read cycle at address XX00h or retrieves the manufacturer

code. A read cycle at address XX01h returns the device code.

A read cycle containing a sector address (SA) and the

address 02h in returns 01h if that sector is protected, or 00h

if it is unprotected. Refer to the Sector Address tables for valid

sector addresses.

The system must write the reset command to exit the autose-

lect mode and return to reading array data.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The program

command sequence is initiated by writing two unlock write

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