PCB2421 datasheet(7/24 Pages) PHILIPS

7 / 24 page

1997 Apr 01

Philips Semiconductors

Preliminary speciﬁcation

1K dual mode serial EEPROM

PCB2421

Table 2

Mode conﬁgurations

Note

1. Where X = don’t care.

6.7

Read operation

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the slave

address is set to logic 1. There are three basic types of

read operations: current address read, random read, and

sequential read.

6.7.1

CURRENT ADDRESS READ

The PCB2421 contains an address counter that maintains

the address of the last word accessed, internally

incremented by one. Therefore, if the previous access

(either a read or write operation) was to address ‘n’, the

next current address read operation would access data

from address n + 1. Upon receipt of the slave address with

R/W set to logic 1, the PCB2421 issues an acknowledge

and transmits the eight bit data word. The master will not

acknowledge the transfer but does generate a STOP

condition and the PCB2421 discontinues transmission

(see Fig.10).

6.7.2

RANDOM READ

Random read operations allow the master to access any

memory location in a random manner. To perform this type

of read operation, the word address must first be set. This

is done by sending the word address to the PCB2421 as

part of a normal write operation. After the word address is

sent, the master generates a REPEATED START

condition following the acknowledge. This terminates the

write operation, but not before the internal address pointer

is set. The master then issues the control byte again but

with the R/W bit set to logic 1. The PCB2421 will then issue

an acknowledge and transmits the 8-bit data word.

The master will not acknowledge the transfer but does

generate a STOP condition and the PCB2421

discontinues transmission (see Fig.11).

6.7.3

SEQUENTIAL READ

Sequential reads are initiated in the same way as a

random read except that after the PCB2421 transmits the

first data byte, the master issues an acknowledge as

DDC

MODE

DCC1

X(1)

DCC2

R/W

opposed to a STOP condition in a random read.

This directs the PCB2421 to transmit the next sequentially

addressed 8-bit word. To provide sequential reads the

PCB2421 contains an internal address pointer which is

incremented by one at the completion of each operation.

This address pointer allows the entire memory contents to

be serially read during one operation.

6.8

Pin description

6.8.1

SDA

This pin is used to transfer addresses and data into and

out of the device, when the device is in the bidirectional

(I2C-bus, DDC2B) mode. In the transmit-only mode

(DDC1), which only allows data to be read from the device,

data is also transferred on the SDA pin. This pin is an

open-drain terminal, therefore the SDA bus requires a

pull-up resistor connected to VDD (typically 10 kΩ for

100 kHz). See brochure

“The I2C-bus and how to use it”

(order no. 9398 393 40011) or

“Data Handbook IC12”.

6.8.2

SCL

This pin is the clock input for the bidirectional mode

(I2C-bus, DDC2B), and is used to synchronize data

transfer to and from the device. It is also used as the

signalling input to switch the device from the transmit-only

mode to the bidirectional mode. It must remain HIGH for

the chip to continue operation in the transmit-only mode

(DDC1).

6.8.3

VCLK

This pin is the clock input for the transmit-only mode

(DDC1). In the transmit-only mode, each bit is clocked out

on the rising edge of this signal. In DDC2B mode, this input

is a don’t care.

6.8.4

This pin is used to inhibit writing of the EEPROM. When

this pin is connected to ground, writing of the EEPROM is

inhibited. When connected to VDD (and VCLK = VDD), the

EEPROM can be programmed. WP may not be left

open-circuit. WP input is a ‘don’t care’ in DDC1 mode.

6.8.5

TEST

Pins 1 is a TEST pin for factory use only. It must be

connected to VDD in the application.

6.8.6

.C.

This pin has no connection and may be tied to VSS, VDD or

left open-circuit.

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