PCD5032 datasheet(8/24 Pages) PHILIPS

8 / 24 page

1997 Apr 03

Philips Semiconductors

Product speciﬁcation

ADPCM CODEC for digital cordless

telephones

PCD5032

FUNCTIONAL DESCRIPTION

7.1

Digital interfaces

7.1.1

ADPCM INTERFACE

The ADPCM receive and transmit data pins, RAD and

TAD, carry 4-bit words of serial data. The received and

transmitted data are controlled separately by the

synchronization pins RAS and TAS.

On detection of a HIGH level on RAS (with a rising edge

on DCLK), the receiver will read 4 ADPCM bits on the next

4 HIGH-to-LOW transitions of DCLK. Likewise, on

reception of a HIGH level on TAS, the transmitter will

output 4 ADPCM bits on the next 4 LOW-to-HIGH

transitions of DCLK. Figure 4 is the ADPCM timing

diagram. During the time that the ADPCM data output

(TAD) is not activated, it will be in a high-impedance state,

enabling a bus structure to be used in a multi-line base

station. Input RAD has an internal pull-down resistor.

The minimum frequency on the DCLK input is 1

⁄54fCLK.

The maximum value equals the clock frequency, and any

value in between may be chosen. The RAS signal controls

the start of each conversion in a frame at an 8 kHz rate.

The master clock ‘CLK’ must be locked to the frequency of

‘RAS’, with a ratio fCLK = 432 × fRAS.

7.1.2

PCM INTERFACE

To enable additional data processing in a base station

both transmit and receive linear PCM data paths are

accessible.

For the receive direction the PCM data is output on pin PO

and read from pin RPI. For the transmit direction the PCM

data is output on pin PO and read from pin TPI. To enable

bus structures to be used in base stations the PCM output

PO is in high-impedance state when not active. Inputs TPI

and RPI have internal pull-down.

In a typical handset application, pin PO is directly

connected to RPI and TPI. If additional data processing is

required (echo cancellation in a base station, for example),

a data processing unit may be placed between PO and

RPI or between PO and TPI.

The data format is serial, 2’s complement, MSB first. PO

outputs 16 bits (14 data bits followed by 2 zeroes). TPI and

RPI read 14 data bits. The bit frequency is 3456 kHz

(CLK). Data output PO changes on the falling edge of CLK

(see Figs. 5 and 6).

For interfacing to digital signal processors, signals TPE

and RPE (both active LOW) mark the position of the

transmit and receive PCM data on pin PO (see Fig.7).

TPE and RPE change on the rising edge of CLK.

Outputs RPE and TPE have low impedance only from half

a CLK cycle after the active state. The rest of the time they

are in high impedance state. Thus a wired-OR

configuration can be made when only one DSP serial input

port is used for reading both transmit and receive data.

An external pull-up is required.

handbook, full pagewidth

MGK073

DCLK

RAS/TAS

RAD/TAD

MSB

LSB

Fig.4 ADPCM timing.

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