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ADC3683 Datenblatt(PDF) 21 Page - Texas Instruments |
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ADC3683 Datenblatt(HTML) 21 Page - Texas Instruments |
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21 / 70 page ![]() 7.3.2.2 Signal Acquisition Time Adjust The ADC3683-SP includes a register (DLL PDN (0x11, D2) which increases the signal acquisition time window for clock rates below 30 MSPS from 25% to 50% of the clock period. Increasing the sampling time provides a longer time for the driving amplifier to settle out the signal which can improve the SNR performance of the system. When powering down the DLL, the acquisition time tracks the clock duty cycle (50% is recommended). Table 7-1. Acquisition time vs DLL PDN setting SAMPLING CLOCK FS (MSPS) DLL PDN (0x11, D2) ACQUISITION TIME (tACQ) 65 0 TS / 4 ≤ 30 1 TS / 2 www.ti.com ADC3683-SP SBASAB5 – MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: ADC3683-SP |
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