TCS3772 datasheet(34/51 Pages) OSRAM

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ams Datasheet

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[v1-01] 2018-Mar-14

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TCS3772 − Register Description

Configuration Register (0x0D)

The CONFIGURATION register sets the wait long time

Figure 40:

Configuration Register

APERS

3:0

Clear Interrupt persistence. Controls rate of Clear channel interrupt to the host

processor.

FIELD VALUE

INTERRUPT PERSISTENCE FUNCTION

0000

Every RGBC cycle generates an interrupt

0001

1 clear channel value outside of threshold range

0010

2 clear channel consecutive values out of range

0011

3 clear channel consecutive values out of range

0100

5 clear channel consecutive values out of range

0101

10 clear channel consecutive values out of range

0110

15 clear channel consecutive values out of range

0111

20 clear channel consecutive values out of range

1000

25 clear channel consecutive values out of range

1001

30 clear channel consecutive values out of range

1010

35 clear channel consecutive values out of range

1011

40 clear channel consecutive values out of range

1100

45 clear channel consecutive values out of range

1101

50 clear channel consecutive values out of range

1110

55 clear channel consecutive values out of range

1111

60 clear channel consecutive values out of range

321

Reserved

WLONG

Reserved

Fields

Bits

Description

Reserved

7:2

Reserved. Write as 0.

WLONG

Wait Long. When asserted, the wait cycles are increased by a factor 12× from

that programmed in the WTIME register.

Reserved

Reserved. Write as 0.

Field

Bits

Description

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