SN74F125

QUADRUPLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SDFS016B – JANUARY 1989 – REVISED JULY 2002

1

POST OFFICE BOX 655303

Memory Address Registers

description/ordering information

The SN74F125 features independent line drivers

with 3-state outputs. Each output is disabled when

the associated output-enable (OE) input is high.

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – N

Tube

SN74F125N

SN74F125N

SOIC

D

Tube

SN74F125D

F125

0

°C to 70°C

SOIC – D

Tape and reel

SN74F125DR

F125

SOP – NS

Tape and reel

SN74F125NSR

74F125

SSOP – DB

Tape and reel

SN74F125DBR

F125

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

FUNCTION TABLE

(each buffer)

INPUTS

OUTPUT

OE

A

Y

L

H

H

L

LL

H

X

Z

Copyright

 2002, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D, DB, N, OR NS PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1OE

1A

1Y

2OE

2A

2Y

GND

4OE

4A

4Y

3OE

3A

3Y