Philips Semiconductors Programmable Logic Devices

Product specification

PLS100/PLS101

Programmable logic arrays

(16

× 48 × 8)

October 22, 1993

50

LOGIC DIAGRAM

NOTES:

1.

All AND gate inputs with a blown link float to a logic “1”.

2.

All OR gate inputs with a blown fuse float to logic “0”.

3.

Programmable connection.

(LOGIC TERMS–P)

9

8

7

6

5

4

3

2

10

11

12

13

15

16

17

18

I0

I1

I2

I3

I4

I5

I6

I7

F0

F1

F2

F3

F4

F5

F6

F7

47

40 39

32 31

24 23

16

S0

S1

S2

S3

S4

S5

S6

S7

X0

X1

X2

X3

X4

X5

X6

X7

8 7

0

27

26

25

24

23

22

21

20

I8

I9

I10

I11

I12

I13

I14

I15

19

CE

15