DS-0033 Sep 05

External-Free Release

Page 2

OXCB950

OXFORD SEMICONDUCTOR LTD.

1

PERFORMANCE COMPARISON............................................................................................................ 5

1.1

IMPROVEMENTS OF THE OXCB950 OVER DISCRETE SOLUTIONS: .......................................................................... 5

2

BLOCK DIAGRAM ................................................................................................................................... 6

3

PIN INFORMATION.................................................................................................................................. 7

4

PIN DESCRIPTIONS ................................................................................................................................ 8

5

CONFIGURATION & OPERATION .......................................................................................................12

6

PCI TARGET CONTROLLER ................................................................................................................ 13

6.1

OPERATION ..................................................................................................................................................................... 13

6.2

CONFIGURATION SPACE............................................................................................................................................... 14

6.2.1

CARDBUS / PCI CONFIGURATION SPACE REGISTER MAP ................................................................................... 14

6.3

ACCESSING THE UART FUNCTION............................................................................................................................... 16

6.3.1

CARDBUS/PCI ACCESS TO THE INTERNAL UART .................................................................................................. 16

6.4

ACCESSING LOCAL CONFIGURATION REGISTERS................................................................................................... 17

6.4.1

LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00) ........................................................ 17

6.4.2

MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04) ............................................................ 18

6.4.3

UART MIRROR REGISTER ‘UMR’ (OFFSET 0X08):................................................................................................... 19

6.4.4

GLOBAL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X0C) ............................................... 20

6.5

CARDBUS/ PCI INTERRUPT ........................................................................................................................................... 21

6.6

CARDBUS/PCI POWER MANAGEMENT ........................................................................................................................ 22

6.6.1

POWER MANAGEMENT VIA UART/ MIO PINS .......................................................................................................... 22

6.6.2

POWER REPORTING .................................................................................................................................................. 23

6.6.3

CARDBUS POWER MANAGEMENT ........................................................................................................................... 24

6.7

CARDBUS STATUS REGISTERS.................................................................................................................................... 25

6.8

CARDBUS TUPLE INFORMATION.................................................................................................................................. 27

7

INTERNAL 950 UART............................................................................................................................ 28

7.1

OPERATION – MODE SELECTION ................................................................................................................................. 28

7.1.1

450 MODE..................................................................................................................................................................... 28

7.1.2

550 MODE..................................................................................................................................................................... 28

7.1.3

750 MODE..................................................................................................................................................................... 28

7.1.4

650 MODE..................................................................................................................................................................... 28

7.1.5

950 MODE..................................................................................................................................................................... 29

7.2

REGISTER DESCRIPTION TABLES ............................................................................................................................... 30

7.3

RESET CONFIGURATION ............................................................................................................................................... 34

7.3.1

HARDWARE RESET .................................................................................................................................................... 34

7.3.2

SOFTWARE RESET..................................................................................................................................................... 34

7.4

TRANSMITTER AND RECEIVER FIFOS ......................................................................................................................... 35

7.4.1

FIFO CONTROL REGISTER ‘FCR’ .............................................................................................................................. 35

7.5

LINE CONTROL & STATUS............................................................................................................................................. 36

7.5.1

FALSE START BIT DETECTION.................................................................................................................................. 36

7.5.2

LINE CONTROL REGISTER ‘LCR’............................................................................................................................... 36

7.5.3

LINE STATUS REGISTER ‘LSR’ .................................................................................................................................. 37

7.6

INTERRUPTS & SLEEP MODE........................................................................................................................................ 38

7.6.1

INTERRUPT ENABLE REGISTER ‘IER’....................................................................................................................... 38

7.6.2

INTERRUPT STATUS REGISTER ‘ISR’....................................................................................................................... 39

7.6.3

INTERRUPT DESCRIPTION ........................................................................................................................................ 39