MPC8541E datasheet(13/84 Pages) FREESCALE

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MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Clock Timing

4.1

System Clock Timing

Table 6 provides the system clock (SYSCLK) AC timing specifications for the MPC8541E.

4.2

TSEC Gigabit Reference Clock Timing

Table 7 provides the TSEC gigabit reference clock (EC_GTX_CLK125) AC timing specifications for the

MPC8541E.

Table 6. SYSCLK AC Timing Specifications

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

SYSCLK frequency

fSYSCLK

—

166

MHz

SYSCLK cycle time

tSYSCLK

6.0

—

SYSCLK rise and fall time

tKH, tKL

0.6

1.0

1.2

SYSCLK duty cycle

tKHK/tSYSCLK

—

SYSCLK jitter

—

+/- 150

4, 5

Notes:

1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK

frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating

frequencies.

2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. For spread spectrum clocking, guidelines are +/-1% of the input frequency with a maximum of 60 kHz of modulation

regardless of the input frequency.

Table 7. EC_GTX_CLK125 AC Timing Specifications

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

EC_GTX_CLK125 frequency

fG125

—

125

—

MHz

EC_GTX_CLK125 cycle time

tG125

—8—

EC_GTX_CLK125 rise time

tG125R

——

1.0

EC_GTX_CLK125 fall time

tG125F

——

1.0

EC_GTX_CLK125 duty cycle

GMII, TBI

RGMII, RTBI

tG125H/tG125

—

%1, 2

Notes:

1. Timing is guaranteed by design and characterization.

2. EC_GTX_CLK125 is used to generate GTX clock for TSEC transmitter with 2% degradation. EC_GTX_CLK125 duty cycle

can be loosened from 47/53% as long as PHY device can tolerate the duty cycle generated by GTX_CLK of TSEC.

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