SZF2002 datasheet(26/76 Pages) PHILIPS

26 / 76 page

1998 Aug 26

Philips Semiconductors

Product speciﬁcation

Low voltage 8-bit microcontroller with

6-kbyte embedded RAM

SZF2002

14.1

ADC Control Register (ADCON)

Table 15 ADC Control Register (SFR address C4H)

Table 16 Description of ADCON bits

Table 17 Selection of analog input channel

14.2

ADC Result Register (ADCH)

Table 18 ADC Result Register (SFR address C5H)

Table 19 Description of ADCH bits

76543210

−−

CKDIV

ADCI

ADCS

AADR2

AADR1

AADR0

BIT

SYMBOL

DESCRIPTION

−

These 2 bits are reserved.

−

CKDIV

Prescaler select. When CKDIV = 1, the ADC clock prescaler is used (divide-by-2).

Prescaling is necessary with clocks over 8 MHz.

ADCI

ADC interrupt ﬂag. This ﬂag is set when an ADC conversion result is ready to be read.

An interrupt is invoked if this is enabled (EAD). This ﬂag must be cleared by software,

(it cannot be set by software).

ADCS

ADC start and status ﬂag. When this bit is set an ADC conversion is started. ADCS

must be set by software. The ADC logic ensures that this signal is HIGH while the ADC

is busy. On completion of the conversion ADCI is set and one clock later the ADCS ﬂag

is reset. ADCS cannot be reset by software.

AADR2

Analog input select. These bits are used to select one of the six analog inputs;

see Table 17.

AADR1

AADR0

AADR2

AADR1

AADR0

SELECTED CHANNEL

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

reserved

76543210

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

BIT

SYMBOL

DESCRIPTION

7 to 0

ADC7 to ADC0

8-bit ADC result

SZF2002 Datenblatt(PDF) 26 Page - NXP Semiconductors

SZF2002 Datenblatt(HTML) 26 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datenblatt Download

Link URL