STPMIC25APQR datasheet(69/145 Pages) STMICROELECTRONICS

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6.2.5

Restart status register (RESTART_SR)

Table 34. RESTART_SR

Reserved

R_RST

R_WDG_FLT

R_TSHDN_FLT

R_OCP_FLT

R_VIN_FLT

R_PKEY_FLT

R_SWOFF

•

Address: 0x04

•

Default: 0b0xxxxxxx where x depends on a power-OFF condition which restarts the PMIC

•

Description: Stores last condition, which restarts the PMIC (power cycle).

The RESTART_SR register is reset in the POWER_DOWN state. Then RESTART_SR is set when going into the

CHECK&LOAD state (see Section 5.4.4: Turn-off conditions and Section 5.1.2: State explanations).

[7]

reserved

[6]

R_RST: Last restart is due to RSTn pin asserted low by the application processor (or by a user

reset button)

0: False

1: True

[5]

R_WDG_FLT: Last restart is due to watchdog hard-fault source while WDG_FLT_CNT <=

WDG_FLT_CNT_MAX.

0: False

1: True

[4]

R_TSHDN_FLT: Last restart is due to thermal shutdown hard-fault source while

TSHDN_FLT_CNT <= TSHDN_FLT_CNT_MAX.

0: False

1: True

[3]

R_OCP_FLT: Last restart is due to regulator overcurrent hard-fault source while OCP_FLT_CNT

<= OCP_FLT_CNT_MAX.

(overcurrent source is saved in OCP_SR1 or in OCP_SR2)

0: False

1: True

[2]

R_VIN_FLT: Last restart is due to VIN falling below VINOK_Fall hard-fault source while

VIN_FLT_CNT <= VIN_FLT_CNT_MAX.

(This is valid only if VIN is kept higher than VINPOR_Fall; or PMIC fully resets)

0: False

1: True

[1]

R_PKEY_FLT: Last restart is due to PONKEYn long key press hard-fault source while

PKEY_FLT_CNT <= PKEY_FLT_CNT_MAX.

0: False

1: True

[0]

R_SWOFF: Last restart is due to a restart request from AP (setting both SWOFF bit and

RREQ_EN bit in MAIN_CR register).

0: False

1: True

STPMIC25

DS14278 - Rev 3

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