ADN2913 datasheet(24/35 Pages) AD

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ADN2913

Data Sheet

Rev. B | Page 24 of 35

DATA

CLOCK

NOTES

1. PHASE REFERS TO SAMPLE_PHASE[3:0]

PHASE = 4

PHASE = 7

PHASE = –4

PHASE = –8

PHASE = 0

(DEFAULT)

Figure 26. Data vs. Sampling Clock

The LOS detector and the slice level adjust can be used simulta-

neously on the ADN2913. Therefore, any offset added to the

input signal by the slice[6:0] bits does not affect the LOS detector

measurement of the absolute input level.

LOS Power-Down

By default, the LOS detector is enabled and consumes power.

The LOS detector is placed in a low power mode by setting

LOS_PDN = 1 (Bit D3 in Register 0x9).

LOS Threshold

The LOS threshold has a range between 0 mV and 128 mV and

is set by writing the number of millivolts (mV) to Register 0x36

followed by toggling the LOS_ENABLE bit in Register 0x74

while LOS_ADDRESS is set to 1. The following is a procedure

for writing the LOS threshold:

Write 0x21 to LOS_CTRL (Register 0x74).

Write the desired threshold in millivolts to LOS_DATA

(Register 0x36).

Write 0x31 to LOS_CTRL (Register 0x74).

Write 0x21 to LOS_CTRL (Register 0x74).

The LOS threshold can be set to a value between 0 mV and

63 mV in 1 mV steps and from 64 mV to 128 mV in 2 mV

steps. In the lower range, all of the bits are active, giving 1

mV/LSB resolution, where Bit D0 is the LSB. In the upper

range, Bit D0 is disabled (that is, D0 = 0), making Bit D1 the

LSB and resulting in 2 mV/LSB resolution.

The LOS_CTRL register contains the necessary address and

write enable bits to program this LOS threshold.

Signal Strength Measurement

The LOS detector measures and digitizes the peak-to-peak

amplitude of the received signal. A single shot measurement is

taken by writing the following sequence of bytes to LOS_CTRL

at Address 0x74: 0x7, 0x17, 0x7. When LOS_ENABLE goes low,

the peak-to-peak amplitude in millivolts is loaded into LOS_

DATA[7:0] (Register 0x36). The contents of LOS_DATA change

only when LOS_ENABLE (Bit D4 in Register 0x74) is toggled

low to high to low while LOS_ADDRESS[2:0] (Bits[D2:D0] in

PASSIVE EQUALIZER

A passive equalizer is available at the input to equalize large

signals that have undergone distortion due to PCB traces, vias,

or connectors. The adaptive EQ functions only at data rates

greater than 5.5 Gbps. Therefore, at rates less than 5.5 Gbps, the

EQ must be manually set.

The equalizer can be manually set using the LA_EQ register

(Register 0x16). An adaptive loop is also available to optimize

the EQ setting based on characteristics of the received eye at the

phase detector. If the channel is known in advance, set the EQ

manually to obtain the best performance; however, the adaptive

EQ finds the best setting in most cases.

Table 22 lists typical EQ settings for several trace lengths. The

values in Table 22 are based on measurements taken on a test

board with simple FR-4 traces. Table 23 lists the typical

maximum reach in inches of FR-4 of the EQ at several data

rates. If a real channel includes lossy connectors or vias, the

FR-4 reach length is lower. For any real-world system, it is

highly recommended to test several EQ settings with the real

channel to ensure the best signal integrity.

Table 22. EQ Settings vs. Trace Length on FR-4

Trace Length (Inches)

Typical EQ Setting

20 to 30

Table 23. Typical EQ Reach on FR-4 vs. Maximum Data

Rates Supported

Maximum Data Rate (Gbps)

Typical EQ Reach on FR-4 (Inches)

0 dB EQ

The 0 dB EQ path connects the input signal directly to the digital

logic inside the ADN2913. The 0 dB EQ is useful at lower data

rates where the signal is large (therefore, the limiting amplifier

is not needed and power can be saved by deselecting the limiting

amplifier) and unimpaired (therefore, the equalizer is not needed).

The signal swing of the internal digital circuit is 600 mV p-p

differential, the minimum signal amplitude that must be provided

as the input in 0 dB EQ mode.

In 0 dB EQ mode, the internal 50 Ω termination resistors can be

configured in one of two ways, either floated or tied to VCC = 1.2 V

(see Figure 31 and Table 27). By setting the RX_TERM_FLOAT

bit (Bit D7 in Register 0x16) to 1, these 50 Ω termination resistors

are floated internal to the ADN2913 (see Figure 35). By setting

the RX_TERM_FLOAT bit to 0, these 50 Ω termination resistors

are connected to VCC = 1.2 V (see Figure 36). In both termination

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