2

February 2007

Document Control #ML0008 Rev 0.7

STK12C68 (SMD5962-94599)

Packages

Pin Descriptions

A0

A1

A2

A3

A4

A5

E

DQ0

DQ1

VCCX

VCAP

DQ2

DQ3

W

A6

A7

VSS

G

DQ7

DQ6

DQ5

DQ4

HSB

A12

A11

A10

A9

28

27

26

25

24

23

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

A8

28-pin SOIC

28-pin DIP

28-pin LCC

Pin Name

I/O

Description

Input

Address: The 13 address inputs select one of 8,192 bytes in the nvSRAM array

I/O

Data: Bi-directional 8-bit data bus for accessing the nvSRAM

E

Input

Chip Enable: The active low E input selects the device

W

Input

Write Enable: The active low W enables data on the DQ pins to be written to the address

location latched by the falling edge of E

G

Input

Output Enable: The active low G input enables the data output buffers during read cycles.

De-asserting G high caused the DQ pins to tri-state.

Power Supply

Power: 5.0V, +10%, -10%

HSB

I/O

Hardware Store Busy: When low this output indicates a Store is in progress. When pulled

low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor

keeps this pin high if not connected. (Connection Optional).

Power Supply

AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from

SRAM to nonvolatile storage elements.

Power Supply

Ground