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PIC18F44J10-E/P Datenblatt(PDF) 13 Page - Microchip Technology |
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PIC18F44J10-E/P Datenblatt(HTML) 13 Page - Microchip Technology |
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13 / 358 page ![]() © 2007 Microchip Technology Inc. Preliminary DS39682C-page 11 PIC18F45J10 FAMILY FIGURE 1-2: PIC18F44J10/45J10 (40/44-PIN) BLOCK DIAGRAM Instruction Decode and Control Data Latch Data Memory (3.9 Kbytes) Address Latch Data Address<12> 12 Access BSR FSR0 FSR1 FSR2 inc/dec logic Address 4 12 4 PCH PCL PCLATH 8 31 Level Stack Program Counter PRODL PRODH 8 x 8 Multiply 8 BITOP 8 8 ALU<8> Address Latch Program Memory (16/32 Kbytes) Data Latch 20 8 8 Table Pointer<21> inc/dec logic 21 8 Data Bus<8> Table Latch 8 IR 12 3 ROM Latch PCLATU PCU PORTE RE2/CS/AN7 RE0/RD/AN5 RE1/WR/AN6 Note 1: CCP2 is multiplexed with RC1 when configuration bit CCP2MX is set, or RB3 when CCP2MX is not set. 2: BOR is not available in PIC18LF2XJ10/4XJ10 devices. W Instruction Bus <16> STKPTR Bank 8 State Machine Control Signals Decode 8 8 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer OSC1 OSC2 VDD, Brown-out(2) Reset Internal Oscillator Fail-Safe Clock Monitor Precision Reference Band Gap VSS MCLR Block INTRC Oscillator Single-Supply Programming In-Circuit Debugger T1OSI T1OSO PORTA PORTB PORTC RA5/AN4/SS1/C2OUT RB0/INT0/FLT0/AN12 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2(1) RC2/CCP1/P1A RC3/SCK1/SCL1 RC4/SDI1/SDA1 RC5/SDO1 RC6/TX/CK RC7/RX/DT RA3/AN3/VREF+ RA2/AN2/VREF-/CVREF RA1/AN1 RA0/AN0 RB1/INT1/AN10 RB2/INT2/AN8 RB3/AN9/CCP2(1) RB4/KBI0/AN11 RB5/KBI1/T0CKI/C1OUT RB6/KBI2/PGC RB7/KBI3/PGD EUSART Comparator MSSP 10-bit ADC Timer2 Timer1 Timer0 CCP2 ECCP1 BOR(2) PORTD RD0/PSP0/SCK2/SCL2 RD1/PSP1/SDI2/SDA2 RD2/PSP2/SDO2 RD3/PSP3/SS2 RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VDDCORE |
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