PIC18F23K20 datasheet(44/420 Pages) MICROCHIP

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PIC18F2XK20/4XK20

DS41303B-page 42

Advance Information

3.1.3

CLOCK TRANSITIONS AND STATUS

INDICATORS

The length of the transition between clock sources is

the sum of:

• Start-up time of the new clock

• Two and one half cycles of the old clock source

• Two and one half cycles of the new clock

Three flag bits indicate the current clock source and its

status. They are:

• OSTS (of the OSCCON register)

• IOFS (of the OSCCON register)

• T1RUN (of the T1CON register)

In general, only one of these bits will be set while in a

given power-managed mode. Table 3-2 shows the rela-

tionship of the flags to the active main system clock

source.

TABLE 3-2:

SYSTEM CLOCK INDICATORS

3.1.4

MULTIPLE FUNCTIONS OF THE

SLEEP COMMAND

The power-managed mode that is invoked with the

SLEEP

instruction is determined by the setting of the

IDLEN bit of the OSCCON register at the time the

instruction is executed. All clocks stop and minimum

power is consumed when SLEEP is executed with the

IDLEN bit cleared. The system clock continues to sup-

ply a clock to the peripherals but is disconnected from

the CPU when SLEEP is executed with the IDLEN bit

set.

3.2

Run Modes

In the Run modes, clocks to both the core and

peripherals are active. The difference between these

modes is the clock source.

3.2.1

PRI_RUN MODE

The PRI_RUN mode is the normal, full power execution

mode of the microcontroller. This is also the default

mode upon a device Reset, unless Two-Speed Start-up

is enabled (see Section 2.10 “Two-Speed Clock

Start-up Mode” for details). In this mode, the OSTS bit

is set. The IOFS bit will be set if the HFINTOSC is the

primary clock source and the oscillator is stable (see

Section 2.2 “Oscillator Control”).

3.2.2

SEC_RUN MODE

The SEC_RUN mode is the mode compatible to the

“clock switching” feature offered in other PIC18

devices. In this mode, the CPU and peripherals are

clocked from the Timer1 oscillator. This gives users the

option of lower power consumption while still using a

high accuracy clock source.

SEC_RUN mode is entered by setting the SCS<1:0>

bits to ‘01’. When SEC_RUN mode is active all of the

following are true:

• The main clock source is switched to the Timer1

oscillator

• Primary oscillator is shut down

• T1RUN bit of the T1CON register is set

• OSTS bit is cleared.

On transitions from SEC_RUN mode to PRI_RUN, the

peripherals and CPU continue to be clocked from the

Timer1 oscillator while the primary clock is started.

When the primary clock becomes ready, a clock switch

back to the primary clock occurs (see Figure 2-7).

When the clock switch is complete, the T1RUN bit is

cleared, the OSTS bit is set and the primary clock is

providing the main system clock. The Timer1 oscillator

continues to run as long as the T1OSCEN bit is set.

OSTS IOFS T1RUN

Main System Clock Source

Primary Oscillator

HFINTOSC

Secondary Oscillator

HFINTOSC as primary clock

LFINTOSC or

HFINTOSC is not yet stable

Note 1: Caution should be used when modifying a

single IRCF bit. If VDD is less than 2.7V, it

is possible to select a higher clock speed

than is supported by the low VDD.

Improper device operation may result if

the VDD/FOSC specifications are violated.

2: Executing a SLEEP instruction does not

necessarily place the device into Sleep

mode. It acts as the trigger to place the

controller into either the Sleep mode or

one of the Idle modes, depending on the

setting of the IDLEN bit.

Note:

The Timer1 oscillator should already be

running prior to entering SEC_RUN mode.

If the T1OSCEN bit is not set when the

SCS<1:0> bits are set to ‘01’, entry to

SEC_RUN mode will not occur until

T1OSCEN bit is set and Timer1 oscillator

is ready.

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