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PIC16F685-E/SS Datenblatt(PDF) 42 Page - Microchip Technology |
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PIC16F685-E/SS Datenblatt(HTML) 42 Page - Microchip Technology |
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42 / 294 page ![]() PIC16F631/677/685/687/689/690 DS41262D-page 40 © 2007 Microchip Technology Inc. 2.2.2.5 PIE2 Register The PIE2 register contains the interrupt enable bits, as shown in Register 2-5. Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 OSFIE C2IE C1IE EEIE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables oscillator fail interrupt 0 = Disables oscillator fail interrupt bit 6 C2IE: Comparator C2 Interrupt Enable bit 1 = Enables Comparator C2 interrupt 0 = Disables Comparator C2 interrupt bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables Comparator C1 interrupt 0 = Disables Comparator C1 interrupt bit 4 EEIE: EE Write Operation Interrupt Enable bit 1 = Enables write operation interrupt 0 = Disables write operation interrupt bit 3-0 Unimplemented: Read as ‘0’ |
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