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CDBCAPTURE Datenblatt(PDF) 3 Page - Cirrus Logic

Teilenummer CDBCAPTURE
Bauteilbeschribung  Data Capture and Interface Board for a PC
PDF  10 Pages
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Hersteller  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CDBCAPTURE Datenblatt(HTML) 3 Page - Cirrus Logic

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CDBCapture+
DS327F1
3
The CDBCapture+ board and software currently
support the following Crystal A/D converter eval-
uation boards:
Data Acquisition Parts via a dual row 10 position
header interface:
Audio Parts via RCA phono jack and optical inputs
for S/PDIF audio data (for sample rates from 30
KHz to 96 KHz):
Future products will be added with software up-
dates.
Software updates are provided with the
Crystal Product Guide CD-ROM and on the Crys-
tal Website at www.crystal.com.
Packaging List:
CDBCapture+ Interface Board
Serial 10 position ribbon cable connector
RS232 Cable
Note: To use the S/PDIF interface, a phono-jack
cable must be purchased from an outside vendor.
The Capture+ evaluation software is installed using
the setup utility provided on the Product Guide CD-
ROM. The location for installation may be any
drive/directory. README and HELP text files are
provided and offer step-by-step instructions on set-
ting up and operating both the hardware and soft-
ware as well as providing information specific to
each supported evaluation board. Once the soft-
ware is installed and launched, the Startup Screen
is displayed on the monitor, as shown in Figure 2.
Pressing the "OK" button starts the software that al-
lows the user to setup the serial port between the
Capture+ module and the PC and configure the
module for a specific A/D converter.
Screens
showing the variety of analysis functions that can
be utilized for evaluation of an A/D converter are
shown and described below.
A Time Domain Analysis is initiated by connecting
a signal source to the evaluation board and acquir-
ing a user-selectable number of samples. The re-
sults of capturing a sine wave are shown in
Figure 3. A reconstruction of the data samples is
displayed, along with the sample count on the hor-
izontal axis and magnitude (A/D counts) on the
CS5012A CS5014
CS5016
CS5101A CS5102A
CS5126
CS5180
CS5181
CS5317
CS5322
CS5501
CS5503
CS5505
CS5506
CS5507
CS5508
CS5509
CS5330
CS5331
CS5334
CS5335
CS5360
CS5390
CS5394
CS5396
SDATA
SCLK
FRAME
5V DC
GND
Serial
Cable
S/PDIF
Link
S/PDIF
Receiver
Programmable
Gate Array
DSP
Boot Code Memory
DSP
Data
Acquisition
Memory
RAM
Led
Display
RS232
to
Host
PC
Figure 1. Functional Block Diagram



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