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NXP Semiconductors

FS23

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

15.1.2 Electrical characteristics

TA = −40 °C to 125 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground.

Symbol

Parameter

Min

Typ

Max

Unit

WAKE1, WAKE2

WAKE12VIL

Digital low-input voltage threshold (falling)

2.0

WAKE12VIH

Digital high-input voltage threshold (rising)

2.97

WAKE12HYST

Hysteresis

100

400

RPD_WAKE12

Pulldown resistance

100

200

400

kΩ

RPU_WAKE12

Pullup resistance

100

200

400

kΩ

TWAKE12_FLT[1]

Wake-up filtering time

• WKx_DGLT = 0

• WKx_DGLT = 1

μs

Table 22. WAKE12 electrical characteristics

[1]

There is no digital filtering when WAKEx input pin is used as a source to control an high-side driver.

15.2 HVIO1, HVIO2

HVIO pins are high-voltage input/output. When these pins are used as input, they can be used as wake-up

sources for the device, alone or in combination with a high-side driver (HSx) for cyclic sense. When configured

as output, the pins provide an open-drain output structure.

15.2.1 HVIO1, HVIO2 used as input

HVIOx pins can be used as simple wake-capable inputs. In this case, when the device is in Normal mode, any

event on the HVIO1 or HVIO2 pins generates a flag (HVIOx_I), when not masked (HVIOx_M). In Low-Power

modes, a wake-up event can be generated on level (high or low) or on a cyclic sense event, depending on

HVIOx_WUCFG[1:0] bits.

When used as a wake-up source, wake-up filtering time is configurable by SPI/I2C using HVIOx_DGLT

bits. Internal pulldown and pullup resistors can be enabled, disabled, or configured as cell repeater as per

HVIOxPUPD_OTP[1:0] bits.

Note: Cell repeater configuration is used to reduce the current consumption. In this configuration, the pullup or

pulldown selection follows the state of the internal buffer output after filtering. If the buffer output is low, pulldown

resistor is selected. If the buffer output is high, the pullup resistor is selected.

When a HVIO pin is used as a global input pin, a a capacitor-resistor-capacitor protection is required. See

Section 25.

HVIO1 or HVIO2 can also be configured as FCCU2 input, to provide MCU or external device error detection in

combination or independently of FCCU1 pin. This mechanism is detailed in Section 19.3.

15.2.2 HVIO1, HVIO2 used as output

HVIO1 and HVIO2 can be configured as open drain outputs by OTP via HVIOx_OUT_EN_OTP bits. In this

case, the output state can be controlled by SPI/I2C using HVIOxHI and HVIOxLO control bits.

HVIO1 and HVIO2 default output state can be configured by OTP using HVIOx_OUT_DFLT_OTP. HVIOx can

also be assigned to one of the slots (SLOT_0/1/2) by OTP using HVIOx_SLOT_OTP. In this case, during power

up, the pin follows the default state as soon as the OTP configuration is loaded in the mirror registers. The pin

state is inverted when the configured slot starts. At power down, the pin goes back to its default value when the

FS23

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7.0 — 16 October 2024

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